Compile bare metal programs and cross tool chains

Give the connector script led. LDS, source file led. s, and makefile

1. Arm-Linux-gcc-g-C led. S-O led. O compilation is not linked and contains debugging information

2. Arm-Linux-LD-tled. LDS-O led. Elf led. O uses the linker script led. LDS for link.

3. Use arm-Linux-objcopy-O binary led. Elf led. bin to convert ELF format to bin

4. Write the generated. binfile to the Development Board.

 

Cross tool chain

1. Cross Compiler

Arm-Linux-gcc-static hello. C-O hello

2. Cross Linker

Arm-Linux-LD-tled. LDS-O led. Elf led. o

3. ELF File tools

Arm-Linux-readelf-A led. Elf where-A is used to view all information, including the size end and running platform.

Arm-Linux-readelf-D led: view the library required for running the LED File

4. Anti-Assembler

Arm-Linux-objdump-d-s Hello> dump

Note: The GCC header file is in/usr/include/stdio. h. The header file of arm-Linux-GCC:/usr/local/ARM/4.3.2/bin/

5. File Format Converter

Arm-Linux-objcopy-O binary led. Elf led. Bin

 

Note: The files generated by arm-Linux-GCC and arm-Linux-LD are in. ELF format and cannot be directly run on arm.

MAKEFILE file'

Rule: describes how to generate the target file.

Targets: prerequisites

Command (use the tab Space key)

Make up a rule

Keyword used for pseudo-targets:

. Phony: Clean ---- indicates that clean is a pseudo target.

Final Goal: if the user does not specify to execute a rule, make will execute the first rule in makefile by default, and the goal in this rule is called the final goal.

Make + target name: The generated target is generated. Execute the separate rule.

--- Variable

Before using variables:

App1: app1.o func1.o func2.o

GCC app1.o func1.o func2.o-O app1

App2: app2.o func1.o func2.o

GCC app2.o func1.o func2.o-O app2

After variables are used

OBJ = func1.o func2.o

App1: app1.o $ (OBJ)

GCC app1.o $ (OBJ)-O app1

App2: app2.o $ (OBJ)

GCC app2.o $ (OBJ)-O app2

You can directly use the default variables.

$ ^: Indicates all dependent files.

[Email protected]: indicates the target

$ <: Indicates the first dependent file.

General rules

%. O: %. s

Arm-Linux-gcc-g-o [email protected]-C $ ^

Echo removal: add the @ symbol before the command (written in makefile)

The make command uses makefile or makefile by default. If neither of the project files is the same, the make-F file name is used.

Compile bare metal programs and cross tool chains