Computer Composition Test Center essay 2

. Two-stage description of the code to write to the diagram

Module fsm2 (OUT,COMP_IN,CLK,CLR)

Input comp_in,clk,clr;

Output out;

Reg[2:0] out;

REG[2:0] CS, NS;

Parameter statea=3 ' b000, stateb=3 ' b001, statec=3 ' b010, stated=3 ' b100;

[Email protected] (Poseedge CLK or Negedge CLR)

Begin If (!CLR)

CS <=stateA;

Else

cs<=ns;

End

[Email protected] (CS or comp_in)

Begin ns=3 ' bx;

Case (CS)

Statea:

Begin

if (!comp_in)

Begin

CS = Statea;

out = 3 ' b001;

End

Else

Begin

CS = Stateb;

out = 3 ' b010;

End

End

STATEB:

Begin

if (!comp_in)

Begin

CS = Stateb;

out = 3 ' b010;

End

Else

Begin

CS = Statec;

out = 3 ' b100;

End

End

Statec:

Begin

if (!comp_in)

Begin

CS = Statec;

out = 3 ' b100;

End

Else

Begin

CS = stated;

out = 3 ' b111;

End

End

stated:

Begin

if (!comp_in)

Begin

CS = stated;

out = 3 ' b111;

End

Else

Begin

CS = Statea;

out = 3 ' b001;

End

End

Endcase

End

Endmodule

. Logic Analyzer Commissioning

How much is the sampled signal?

Related to the number of triggering stages

Sampling clock selects the fastest global clock in the circuit

. Design CPU module, bit width, instruction (description) The introduction of peripheral interface

Use non-blocking assignment in sequential circuits <=

Use blocking assignment in combinational circuits =

Directive Format declaration:

III XXX YYY,

The III represents the instruction, XXX represents the RX register, and the YYY represents the RY register,

Following the MIV instruction followed by the input data is a 16-bit immediate number d.

CPU bit width: 16 bits

Directive Format declaration:

III XXX YYY,

III represents the instruction,

XXX represents the Rx register,

The YYY represents the Ry register,

Following the Miv instruction followed by the input data is a 16-bit immediate number D.

Instruction encoding Table:

000:MV rx,ry//Rx <-[Ry]

001:MVI Rx, #D//Rx <-D

010:add Rx, Ry//Rx <-[rx] + [Ry]

011:sub Rx, Ry//Rx <-[rx]-[Ry]

Port

DIN, Buswires, Resetn, Clock, Run, done

Block

Alu (addsub), Controler, Regn, Mux, Upcount, Dec3to8

Add Peripherals:

Seven Segment Code tube Seg7_scroll

Dial Key Switch Regne

Personal gain and understanding:

1, Learning module call method

A module is like a black box with input and output, in which the process is encapsulated, a reasonable calling module,

With the clock, you can complete the CPU design.

2. Design Ideas

First determine what modules are needed, what functions the module completes, then determine the input and output of the module, and the connection of the input and output

Then, those are the time-series modules that need to be stored, those are the logical modules, determined by the clock and some semaphores to

Control of their behavior.

15. Compilation Interpretation

Instruction encoding Table:

000:MV rx,ry//Rx <-[Ry]

001:MVI Rx, #D//Rx <-D

010:add Rx, Ry//Rx <-[rx] + [Ry]

011:sub Rx, Ry//Rx <-[rx]-[Ry]

100:ld Rx,[ry]: Rx <-[Ry]

101:st Rx,[ry]: Rx--[Ry]

110:MVNZ rx,ry:if G! = 0, Rx <-Ry

1. Numbering conversion

3ab.11 binary 1110101011.00010001 decimal 939.06640625

111.101 binary to decimal 7.625

215 decimal Turn binary 11010111

3AB Hex Turn binary 1110101011

Each binary abbreviation (B D H)

Hex indicates hex

DEC denotes decimal

BIN means binary

Simplification of logical algebra

Truth table

An expression

Logic circuit

Karnaugh map

Waveform diagram

RISC,CLSC difference, what are the differences

Structural features	CISC	Risc
instruction system size and instruction format	Large instruction system, variable instruction format	instruction system Small, instruction format fixed, mostly register-based
Addressing mode	12~24 species	Limiting species
Universal Register and Cache design	General-Purpose Registers 9~24 , basically using one-of-a-command and data caching	Basically use separate instructions and data cache, the number of universal registers
Clock frequency vs CPI	Clock frequency lower	Clock frequency high
CPU Control	Large owning control memory (ROM) for encoding control, also with hard-wired control	Most do not control the memory, but with hard-wired control

Computer Composition Test Center essay 2