Computer system elements-chapter three sequential logic

1 This chapter introduces clocks and triggers to build memory units. A trigger is a memory-capable minimum memory unit that stores a bit bit.
2 When designing a computer clock, the length of the clock cycle is slightly longer than that of a bit in the computer's two physical distance chips.
3 D Flip-flop
4 Registers
1) 1 bit register
/**
* 1-bit Register:
* If load[t] = = 1 then out[t+1] = in[t]
* Else out does no change (out[t+1] = out[t])
*/

CHIP Bit {
In, load;
Out;

PARTS:
Mux (A=OUT1,B=IN,SEL=LOAD,OUT=OUT2);
DFF (IN=OUT2,OUT=OUT1);
and (A=out1,b=true,out=out);
}
2) Register
/**
* 16-bit Register:
* If load[t] = = 1 then out[t+1] = in[t]
* Else out does no change
*/

CHIP Register {
In in[16], load;
Out out[16];

PARTS:
Bit (In=in[0],load=load,out=out[0]);
Bit (in=in[1],load=load,out=out[1]);
Bit (in=in[2],load=load,out=out[2]);
Bit (In=in[3],load=load,out=out[3]);
Bit (In=in[4],load=load,out=out[4]);
Bit (In=in[5],load=load,out=out[5]);
Bit (In=in[6],load=load,out=out[6]);
Bit (In=in[7],load=load,out=out[7]);
Bit (In=in[8],load=load,out=out[8]);
Bit (in=in[9],load=load,out=out[9]);
Bit (in=in[10],load=load,out=out[10]);
Bit (in=in[11],load=load,out=out[11]);
Bit (in=in[12],load=load,out=out[12]);
Bit (in=in[13],load=load,out=out[13]);
Bit (in=in[14],load=load,out=out[14]);
Bit (in=in[15],load=load,out=out[15]);
}
3) RAM8

CHIP RAM8 {
In in[16], load, address[3];
Out out[16];

PARTS:
Dmux8way (IN=LOAD,SEL=ADDRESS,A=A1,B=B1,C=C1,D=D1,E=E1,F=F1,G=G1,H=H1);
Register (IN=IN,LOAD=A1,OUT=OUT1);
Register (IN=IN,LOAD=B1,OUT=OUT2);
Register (IN=IN,LOAD=C1,OUT=OUT3);
Register (IN=IN,LOAD=D1,OUT=OUT4);
Register (IN=IN,LOAD=E1,OUT=OUT5);
Register (IN=IN,LOAD=F1,OUT=OUT6);
Register (IN=IN,LOAD=G1,OUT=OUT7);
Register (IN=IN,LOAD=H1,OUT=OUT8);
MUX8WAY16 (a=out1,b=out2,c=out3,d=out4,e=out5,f=out6,g=out7,h=out8,sel=address,out=out);
}
4) RAM64
CHIP RAM64 {
In in[16], load, address[6];
Out out[16];

PARTS:
Dmux8way (IN=LOAD,SEL=ADDRESS[3..5],A=A1,B=B1,C=C1,D=D1,E=E1,F=F1,G=G1,H=H1);
RAM8 (IN=IN,LOAD=A1,ADDRESS=ADDRESS[0..2],OUT=OUT1);
RAM8 (IN=IN,LOAD=B1,ADDRESS=ADDRESS[0..2],OUT=OUT2);
RAM8 (IN=IN,LOAD=C1,ADDRESS=ADDRESS[0..2],OUT=OUT3);
RAM8 (IN=IN,LOAD=D1,ADDRESS=ADDRESS[0..2],OUT=OUT4);
RAM8 (IN=IN,LOAD=E1,ADDRESS=ADDRESS[0..2],OUT=OUT5);
RAM8 (IN=IN,LOAD=F1,ADDRESS=ADDRESS[0..2],OUT=OUT6);
RAM8 (IN=IN,LOAD=G1,ADDRESS=ADDRESS[0..2],OUT=OUT7);
RAM8 (IN=IN,LOAD=H1,ADDRESS=ADDRESS[0..2],OUT=OUT8);
MUX8WAY16 (a=out1,b=out2,c=out3,d=out4,e=out5,f=out6,g=out7,h=out8,sel=address[3..5],out=out);
}
5) PC counter
/**
* A 16-bit counter with load and reset control bits.
* if (reset[t] = = 1) out[t+1] = 0
* Else if (load[t] = = 1) out[t+1] = in[t]
* Else if (inc[t] = = 1) out[t+1] = Out[t] + 1 (integer addition)
* Else out[t+1] = out[t]
*/

CHIP PC {
In In[16],load,inc,reset;
Out out[16];

PARTS:
Mux16 (a=back,b=in,sel=load,out=in1);
Mux16 (a=in1,b=false,sel=reset,out=in2);
Register (IN=IN2,LOAD=TRUE,OUT=OUT1);
And16 (a=out1,b=true,out=out);
INC16 (IN=OUT1,OUT=OUT2);
Mux16 (A=out1,b=out2,sel=inc,out=back);
}

Computer system elements-chapter three sequential logic