- The content of the controller section is what makes me understand the processor a step further.
- Learn that the assembly is still somewhat abstract, why machine instructions can be directly recognized and executed by the machine?
- This just know, the machine instruction also has micro-program, scrutiny up the most non-point operation should be micro-instructions, a number of micro-instructions to achieve a command function
- Further subdivide the instructions into many stages (called cycles, such as reference cycles, execution cycles, etc.), there is an intermediate level of fragmentation between the micro-instruction and the instruction hierarchy, that is, the function of a number of micro-directives to implement a certain stage of the instruction, such as fetching, reading, etc. The function of the multiple phases of the instruction is composed of the function of the instruction, and several instructions are formed to run the program.
- A micro-instruction as the most basic machine action, as I understand it, a micro-directive indicates which parts need to work in this step, and which do not need to work. Need to work on the "Power on", do not need to "disconnect", the components on the electricity will also run their own, the current flow up, like the door circuit to achieve a variety of logic, the final completion of a micro-instruction operation
- such as the arrangement of the reference period
| beats |
Action |
| C1 |
MAR <-(PC), R <-1 |
| C2 |
MDR <-M (MAR) |
| C3 |
PC <-(PC) +1 |
| C4 |
IR <-(MDR), CU <-op (IR) |
- The beat is the control signal of the timing, and all the movements are under strict control of the timing.
- C1 beats, the content of the PC is the address of the next instruction into the Mar, and the reading signal is 1 valid
- C2 beats reading data from main memory to MDR according to the address of Mar, read an instruction
- C3 beats pc Self add 1, point to next instruction
- C4 the instruction of the MDR is fed into the IR instruction register and the operation code portion of the IR instruction is fed into the CU controller for decoding
- Each "MAR <-(PC)" Trick is done by a micro-command, involving only a few parts. are controlled by electrical signals, then according to my guess, the output of the PC opens, the input to Mar opens, the current flows naturally, and the contents of the PC are sent to Mar. Do not know right, anyway, there are circuit control can be achieved.
Composition and function
- The work of the processor is under the command of the controller Cu, according to the "Take command-analysis instructions-based on addressing the number of operands address-the number of source operations-processing the source operand-write the number of operations," the order of the cycle to explain the instructions.
- The function of CU is that the instruction is analyzed (decoded), and according to the current processor state , a control signal/Command is issued to each part of the computer.
Timing system
- The basis of an orderly operation, i.e. under the control of Time series.
The simple point is that the time interval is specified, each time period to complete the task can be completed, the allocation of two time periods and so on, but time is always the integer multiples of time period.
Instruction Cycle: The time required for the processor to access an instruction from the primary and execute the instruction
- However, the time required for different instructions is different, and the time of the same instruction is affected by the environment, in order to simplify the control , it is generally designed to be an integral multiple of the beat-the reference period
- The base period is called the machine cycle or CPU cycle, depending on the basic operation of the instruction and the operating speed of the period.
- For single-cycle processors, the instruction period for all instructions is the same, which equals a machine cycle.
- In order to ensure the adaptation of all instructions, it is necessary to select the time for the most complex instructions.
- Multi-cycle processor, the cycle of an instruction is divided into several parts to refine, the simplest two-cycle period is divided into "the reference period" and "execution period"
- There must be a benchmark between multiple cycles, and this benchmark is the machine cycle
- In order to ensure that at least one instruction in a machine cycle can complete the basic operation (the refinement of a part), generally choose a time spent a longer period of time (the visit depends on the bus, so the time of the visit is also called the bus cycle)
- A standard, synchronous bus with a bus cycle of 4 beats
Level Three timing
Control mode
- are typically multi-cycle processors. The single cycle, though simple in design, is too wasteful. Good CPU time, mostly idle.
- but in multi-cycle, it is necessary to consider different instructions whose instruction cycles are necessarily different, and it may not necessarily be the same for each part of the instruction division
- Although we use the time of the visit as the machine cycle to ensure that a basic operation can be done within a machine cycle, For example, refer to, Address, execute, interrupt query these four parts, it is necessary to ensure that a machine cycle can complete a part of the Operation
- but for complex operations, such as multiplication, division, the execution period is likely to be greater than the time of a visit, That is, it is not necessary to complete the execution cycle within a machine cycle
- It's embarrassing.
- So we need to control
- Synchronous control: The idea of a single-cycle processor is similar, since the instruction is divided, the longest part of the operating time as a benchmark
- Assuming that the multiplication is the longest and needs to be completed in two machine cycles, it also allocates two machine cycle times for other parts, such as finger, address, etc.
- However, for most operations, the two machine cycles are too long, which results in a CPU that is often in an idle state. Waste waste
- As a means of compensating under the control of synchronization, people have designed the machine cycle of unequal length. The simple operation takes 3 beats of the machine cycle, and the complex operation takes 5 beats of the machine cycle. But above that requires a layer of control over the distribution of machine cycles
- Asynchronous control
- The "Handshake/Answer" method is used to determine the length of the machine cycle. When entering a machine cycle, a corresponding "instruction execution stage flag" is set to 1, when the last micro-operation is completed, a signal is sent to the controller, and the controller sends a signal to set the "instruction execution stage flag" to 0. That's the end of a machine cycle.
- As a result, the length of the machine cycle cannot be specified.
- Joint control
- The combination of the two methods
- For example, in the internal synchronization of parts (such as the Alu), the parts are asynchronous
- For example, the length of the machine cycle is fixed, but depending on the complexity of the instruction, the number of machine cycles allocated for each instruction will vary. This is a joint control, synchronous (machine cycle fixed length) in asynchronous, asynchronous in sync (different instruction cycles have different number of machine cycles)
Hard wiring and micro-programs
- At last the part of the micro-command.
- Said, an instruction is translated by the controller into a number of micro-instructions (also known as micro-operation, but the micro-directive "instruction" level of the concept especially corresponds to the micro-program, because the hard wiring is not involved in the "instruction" level), and an instruction itself can be divided into multiple parts, then each part also corresponds to a number of micro
Hard wiring
Principle
- Each micro-operation corresponding to the need to use the components, signals are connected with the logic circuit, and so on the appropriate signal to automatically start the corresponding components (power on ... Switch to open ... or the like) ...
For example, for the reference period, usually to arrange a machine cycle time is sufficient, the usual machine cycle is 4 beats, that is, 4 beats to complete the reference operation
| beats |
Action |
| C1 |
MAR <-(PC), R <-1 |
| C2 |
MDR <-M (MAR) |
| C3 |
PC <-(PC) +1 |
| C4 |
IR <-(MDR), CU <-op (IR) |
- For each micro-operation, list which cycle of the instruction it is in, which beat, which instructions need to be used
| Cycle |
beats |
Micro Instructions |
SHL |
Ldam |
STAM |
JMP X |
JZ X |
ADD M |
COM |
| FE |
C1 |
MAR <-(PC) |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
| FE |
C1 |
R <-1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
| FE |
C2 |
MDR <-M (MAR) |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
| FE |
C3 |
PC <-(PC) +1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
| FE |
C4 |
IR <-(MDR) |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
| FE |
C4 |
CU <-OP (IR) |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
| Exe |
C1 |
MAR <-ad (IR) |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
| ... |
... |
... |
... |
... |
... |
... |
... |
... |
... |
| Exe |
C2 |
MDR <-M (MAR) |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
| ... |
... |
... |
... |
... |
... |
... |
... |
... |
... |
- It's too long for me to write.
- Take "mdr<-m (MAR)" as an example, that is to read the main memory content of micro-operation
- As can be seen from the table, the C2 beats in the reference period Fe are arranged for this micro operation, and the C2 beats in the execution period EXE also have this operation
- Because the reference period is necessary (all instructions are used), that is, as long as the C2 beat of the reference cycle, then the micro-operation will have to start the execution
- The execution cycle is different, some instructions need to be from the main access number, and some instructions do not need, but as long as necessary, is arranged in the C2 beat. That is, to the C2 beat of the execution cycle, if it is required from the primary access number of instructions, then this micro-operation will also be initiated execution
- So for all the micro-operation, is arranged in advance, you you in which cycle which beats, he again in which cycle of which beats, from instruction to micro-operation sequence, also need to conform to the table of the order of the micro-operations specified
- Only the simplest two-week period is used here for example.
- Before designing the combinational circuit, we also write out the logical expression corresponding to the micro-operation.
- such as "Mdr<-m (MAR)"
- Fe C2 (SHL + LDA m + STA m + JMP x + JZ x + COM) + exe C2 (LDA M)
- = Fe C2 + exe C2 (LDA M)
- = C2 [FE + exe (LDA M)]
- Note: Logical Plus and logical multiplication
- FE, C2 are current status signals, which cycle, which beats
- For the LDA m signal, it is naturally the signal that the ID instruction decoder is going to send, which is to determine which instruction the current instruction is.
- The output at this time is just that I'm going to start the micro-operation "Mdr<-m", which translates the current instruction into a micro-operation sequence based on the timing.
- Then this output corresponds to the corresponding control signal, also by the logic circuit to correspond.
According to my (guess) solution (think), each micro-operation corresponds to a plurality of parts, then to achieve this micro-operation requires that each corresponding component will emit a control signal, this control signal is called micro-command . It's pretty much the bottom of the order. However, it should be possible to continue the translation of the corresponding parts (it should be), such as the signal to the ALU is to tell it what to do, whether add or subtract or shift, and so on, the ALU received the signal after the translation of the corresponding action to understand.
From Baidu Encyclopedia to steal a picture
Micro Program
- Principle
- since each micro-directive needs to emit a control signal is the same , then stored down, when used to directly take out the use of it can be. Wit!
- Compared to hard wiring, the complexity of its hardware is greatly reduced, but also need to be removed from the location of micro-instructions, so it will take more time than the direct use of logical circuit of the hard wiring to slow
- For RISC or hard wiring method is more cost-effective, because RISC itself instruction is not much, hardware complexity is not high to where to
- History
- In fact, as early as 1951 this idea was put forward by computer Professor Wilkes of Cambridge University, so "Micro program Control" is also called "Wilkes Model"
- However, the memory at that time was too slow and slow,,,,,,,,,,,,
- Design
- The same time, according to the cycle, the beat to specify when each micro-instruction will be executed.
- The micro-instructions are programmed into micro-programs
- Put all the micro-programs into a rom--control memory cm inside the controller, (control memory, referred to as the deposit)
- When the machine is running, the controller takes out the corresponding micro-instructions according to the current instruction, state (beat), and feeds into the control data register in accordance with the well-defined beats. Cmdr
- A micro-command (i.e. a control signal) is issued by the Cmdr to notify the corresponding part to start working
- Micro Program Controller composition
- The original controller of the IR, the PC is still saved, see the rest
- The micro-address formation logic replaces the function of implementing the instruction decoder.
- Micro-instruction register holds current micro-instructions
- The control memory stores all micro-instructions in the form of a micro-program
- The micro-instruction address register (UAR) stores the address of the micro-instruction, also known as Cmar
- Micro-programs and micro-instructions
- Micro Program
- Typically, a micro-program can perform a basic operation, such as a reference operation can be programmed into a micro-program. And to think that public operations can only store one copy, which is basically the three common parts of the reference, address, and interrupt judgment.
- For each of the other directives, the micro-instructions of its executing part are necessarily different, and each instruction needs to correspond to an executing part of the micro-program
- In general, n directives require the preparation of N+3 micro-programs
- Micro Instructions
- Consists of the Action control field and the Order control field
- The Action control field records the micro commands that need to be issued, because they are prepared in advance, and these micro-commands can be used to perform the operation of this micro-instruction.
- The "Order control field" is used to determine the address of the next micro-instruction, if the current micro-program is not completed, the general Order plus 1 points to the next micro-instruction. If the execution is done, then the equivalent of telling the micro-address formation logic, my current micro-program execution, should choose the next micro-program execution. This is usually done by setting the appropriate flag bit. Therefore, according to the current instruction opcode, timing to determine which of the next micro-program. The indicated micro program is executed, if the current instruction requires an address to jump to the address of the micro-program, do not need to jump directly to the execution of the current instruction of the micro-program
- Detail Micro Instructions
- Action Control field: Record the control signal to be emitted, there are different encoding methods
- Direct representation
- each digit corresponds to a control signal, if the bit is 1 means to emit this control signal, 0 does not issue the
li> but the control signal is too damn much. It's easy to loosen hundreds. A directive is reluctant to occupy a few, a micro-directive will occupy hundreds of. No way!
- coded notation
- so it means the code.
- but only the control signals that are mutually exclusive (cannot be emitted simultaneously) can be encoded
- There is also a coded nature Decode
- Field Direct encoding
-
- field Indirect encoding
-
- Order Control field
- also called "Next address"
- not all the time need to use the next address of the Micro command
- Power on, the address of the first micro-instruction is generated by a specialized circuit
li> the end of the last micro-command of an instruction, then the next one must be the reference period of the micro-program, there is a specialized circuit generation
- generally by the last micro-instruction of the reference period micro-command to set the "site Mark Ind" is 1, indicating the next step to enter the address period of the instruction, Because the site is a public operation, there is also a specialized circuit generation
- if a micro-command set the "Execute Flag exe" to 1, indicating to enter the execution period, the next address is formed by the micro-address logic based on the instruction opcode. Since the location of the micro program stored in CM is fixed, a ROM can be set up to store the first address of each micro-program, and each instruction opcode corresponding to the first address of the micro-program in the ROM storage address for this instruction opcode, That is, the instruction opcode (is a binary code) as the address (all the instruction opcode is not the same) to access the ROM can be quickly obtained this instruction opcode the corresponding micro program in CM address ~
- The method to give the following address
- gives directly: The current is a, the next address is usually B, unless the current micro-program execution ends, it is unconditionally transferred to B. If the execution end is bound to enter the interrupt, you can directly give the
- increment count: The UAR is given to automatically add 1 features, so that can meet all the order of micro-instructions, for branch/jump, you need to improve the order control field, divided into "Transfer control field BCF" and "Transfer Address field BAF", If the condition is satisfied, use BAF to rewrite the uar
- assertion: The Order control field is divided into "non-Test field" and "Test field"
- "Non-Test field" directly constitute the next address of the high-level
- "test Fields "and" Non-test fields "as well as status (timing, etc.), instruction opcode, etc. into the" test network "to generate the status of the next address
- this supports multiplexing, where the number of transfers is determined by the digits of the" test field "(N bits have 2^n)
- This week, the school elective course requirements, read a book called "The World is flat", although it has been published for a long time, but it is still worth reading.
Computer. The machine needs to be controlled. Controller CU
