Concept of Circuit common sense (8)-principle diagram of MOS and simple CMOS Logic Gate Circuit

Modern single-chip microcomputer is mainly made of CMOS technology. 1. MOSThere are two types of MOS: N and P. As shown in: Take the n-type tube as an example. The 2-end is the control end, called the "Gate"; the 3-end is usually grounded, called the "source pole"; the source pole voltage is recorded as VSS, and the 1-end is connected to the positive voltage, it is called "Drain pole", and the drain voltage is recorded as VDD. To enable the connection between one and three ends, a high level must be added to Gate 2. For a P-type tube, the gate, source pole, and drain pole are 5 ends, 4 ends, and 6 ends respectively. To enable the connection between 4 and 6 ends, the Gate 5 must be low. In a logical device or single chip microcomputer made of CMOS technology,N-type tubes and p-type tubes are usually paired.. The two CMOS tubes that appear at the same time,At any time, as long as one is turned on, the other is not turned on(That is, "cutoff" or "shutdown"), soIt is called a complementary CMOS tube ". 2. CMOS logic level Power supply voltage of High-speed CMOS circuitVDD is usually + 5 V; VSS is grounded, Which is 0 V. HighIt is regarded as the logic "1", and the range of the level value is 65% ~ of VDD ~ VDD (or VDD-1.5V ~ VDD) Low LevelIt is regarded as "0" and must not exceed 35% or 0 ~ of the VDD ~ 1.5 V. + 1.5v ~ + 3.5v should be regarded as an uncertain level. Avoid uncertain levels in hardware design. In recent years, with the development of sub-micron technology, the power supply of single chip microcomputer is declining. Low Power Supply voltage helps reduce power consumption. A large number of CMOS devices whose VDD is 3.3v have been used. In portable applications, 2.7 V or even V single-chip microcomputer has also appeared. In the future, the power supply voltage will continue to decrease to 0.9 V,The level lower than 35% of VDD is regarded as the logic "0", and the level higher than 65% of VDD is regarded as the logic "1 ".. 3. Non-Portal Non-door (reverse) is the simplest door circuit, composed of a pairCMOSManagement. Its working principle is as follows: A In high-power scenarios, P Type Tube deadline, N Type Pipe conduction, output end C Level and VSS Consistent, low output level; A Low-Power period, P Type Pipe conduction, N Type Pipe cutoff, output end C Level and V Dd Consistent, output high level. 4. Non-Portal Working principle: ①, A , B The input is low-power, 1 , 2 Pipe conduction, 3 , 4 Deadline, C Terminal Voltage and V Dd Consistent, output high level. ②, A Input high level, B Low input power, 1 , 3 Pipe conduction, 2 , 4 Deadline, C Terminal potential and 1 The drain pole of the tube remains the same, and the output is high. ③,AInput low level,BWhen the input is high, it is similar to ②, and the output is high. ④, A , B The input is normal, 1 , 2 Deadline, 3 , 4 Pipe conduction, C The end voltage is the same as that of the ground, and the output is low. 5. or not Or non-gate Working principle: ①, A , B The input is low-power, 1 , 2 Pipe conduction, 3 , 4 Deadline, C Terminal Voltage and V Dd Consistent, output high level. ②, A input high level, B low input 1 , 4 pipe conduction, 2 , 3 pipe cutoff, C the output is low. ③,AInput low level,BWhen the input is high, it is similar to ②, and the output is low. ④, A , B The input is normal, 1 , 2 Deadline, 3 , 4 Pipe conduction, C The end voltage is the same as that of the ground, and the output is low. Note: Remove the small circle at the output end of the above-mentioned "Non" Door, "or" Non "Door logical symbol to form the logical symbol of" with "Door," or "door. The circuit diagram that implements the "with", "or" function must be added with a reverser at the output end, that is, a pairCMOSManagement, therefore,The "and" door is actually more complex than the "and" door, and the delay is longer.This should be noted in circuit design. 6. Three-State Gate How the Three-mode gate works: When the control end C For 1 , N Type Tube 3 Turn on, at the same time, C The end level becomes a low level through the reverser. P Type Tube 4 Conduction, input A The level 3 , 4 PIPE to output end B . When the control end C For 0 , 3 , 4 All management ends, input end A Level status cannot reach the output end B , Output end B A high-resistance state is called a high-resistance state ". This device is also known as a transmission door with a control end.". Three-state gates with certain driving capabilities are also called "buffers", and the logical symbols are the same. Note: From the CMOS equivalent circuit, truth table, and logic expression, we can see that the "0" and "1" are changed to the "or not" gate. For "1", the valid signal is "non", and for "0", the valid signal is "or not. The logical device symbols shown in the preceding figure are the input and output relationships under the positive logic, that is, they are effective for "1" (high level. Most of the control signals in single-chip microcomputer are defined according to negative (low-level. For example, the chip selection signal CS (chip select) indicates that when the signal is "0", it indicates that the chip is selected. Therefore, the logical symbols of the "or not" gate can also be drawn. 7. Integrated Logic Circuit Different combinations of Logical Circuits such as non-or non-gate, or non-gate can be used to obtain various combinations of Logical Circuits, such as decoder, decoder, and multi-channel switch. You can use existing integrated circuits or programmable logical devices, such as pal and gal, to implement integrated logic circuits.