Configurations of S3C2440 Serial Communication

 

The relevant registers for UART configuration are listed as follows (listed in the order in the S3C2440 manual ):

1. ulconn register: Linear Control Register

Function: sets the parity check, stop bit, and data bit (5-8 digits)

Note: Generally, it is set to no-check, one stop bit, and the data bit is 8 bits, which is commonly referred to as "8n1". At this time, the register value is 0x3. (Bit [6] = 0 indicates the normal mode; otherwise, it indicates the infrared mode );

2. UConn register: Channel n controller

Function: select the UART clock source and set the UART interrupt mode.

Note: You can select pclk, uextclk, or fclk/n. Bit [5] = 1 is the return mode for testing. Bit [3: 2] and bit [0-1] control the transmission and receipt modes respectively. This mode is often set for beginners to interrupt requests or query modes, bit [3: 2] = bit [1:0] = 01.

3. ufconn register: FIFO control register

Function: it is used to set whether to use FIFO. It is used to set the trigger threshold of each FIFO, that is, the number of data in the FIFO sending is interrupted, and the number of data in the FIFO receiving is interrupted. You can reset each FIFO by setting the ufconn register. Read the ufstatn register to check whether each FIFO is full and how much data is there.

NOTE: If bit [0] = 1, the FIFO mode is enabled. Otherwise, the FIFO mode is disabled. Do not use FIFO for beginners

4. umconn register: UART Modem Control Register

Note: bit [4] = 0, the AFC is invalid

5. ubrdivn register: baud rate division register

Function: sets the baud rate.

Note: ubrdivn = (INT) (UART clock/(baud rate * 16)-1;

UART clock: pclk, fclk/N or uextclk. For example, if the baud rate is 115200bps and the UART clock is 40 MHz, ubrdivn is:

Ubrdivn = (INT) (40000000/(115200*16)-1 = (INT) (21.7)-1 (take the nearest integer) = 22-1 = 21.

5. utrstatn register: receiving/sending Status Register

Function: displays the status of the receiving/sending cache register.

Note: In non-FIFO mode, bit [0] = 1 indicates that the data is received; bit [1] = 1 indicates that the sending cache register is empty. For more information about the ufstat register bit in FIFO mode, see the manual.

6. uerstatn register: Error Status Register

Function: Indicates whether errors occur.

Note: beginners may not pay attention to their status. When they are studying in depth, they can check the relevant information.

7. ufstatn register: FIFO Status Register

Function: indicates the status of FIFO.

Note: bit [14] = 1 indicates that the sending of FIFO is full and data cannot be sent for the time being. Bit [6] = 0, indicating that there is data in the receiving FIFO (personal understanding, but not rigorous ).

8. umstatn register: UART modem Status Register

Note: For Beginners

9. utxhn register: sending cache register

Function: The UART is saved to the buffer and automatically sent out.

Note: bit [] = sends data.

10. urxhn register: receiving cache register

Function: When the UART receives the data, the CPU reads this register to obtain the data.

Note: bit [] = receives data;

Note: urxhn and utxhn are divided into large and small ends. You should pay attention to them when defining registers. However, they generally use the small-end method.

 

Take serial port 0 as an example: fclk = 400 m, fclk: hclk: pclk =; baud rate is 115200

Note: It is particularly important that gphcon related to serial communication should be configured. This is easy for beginners to ignore. I have ignored it, so that serial communication cannot be implemented and the reason is finally found.

Void port_init (void)

{

Gphcon = 0x00faaa;

Gphup = 0x7ff;

}

Void uart_init (void)

{

// Mode 1

/****** Pclk is used as UART's clock ****************/

/***** No FIFO ---********************************* ****/

# If 1

Ulcon0 = 0x3; // 8n1

Ucon0 = 0x245; // pclk serves as the serial clock

Ufcon0 = 0x0; // No FIFO

Umcon0 = 0x0; // AFC disable

Ubrdiv0 = 26;

/*************************************** ***********/

# Endif

 

// Mode 2

/********************* Loop_uart-pclk-noFIFO *************/

# If 0

Ulcon0 = 0x3; // 8n1

Ucon0 = 0x265; // bit [5] control loop mode: 1 is valid

Ufcon0 = 0x0; // No FIFO

Umcon0 = 0x0; // AFC disable

Ubrdiv0 = 26;

 

/********************* Loop_uart **************** ****/

# Endif

 

// Mode 3

/******************** UART -- FIFO--PCLK ************** *****/

 

# If 0

Ulcon0 = 0x3; // 8n1

Ucon0 = 0x245; // pclk serves as the serial clock

Ufcon0 = 0x31; // bit0] = 1 indicates enable FIFO

Umcon0 = 0x0; // AFC disable

Ubrdiv0 = 26;

 

/*************************************** ***/

# Endif

}

Note: The definition is as follows:

# Define wrutxh0 (CH) (* (volatile unsigned char X) 0x50000020) = (unsigned char) (CH)

# Define rdurxh0 () (* (volatile unsigned char *) 0x50000024)

When Mode 1 and Mode 2 are used, the input and output functions can be in the following form:

Char uart_get_char (void)

{

While (! (Utrstat0 & 0x1); // receive data ready

Return (char) (rdurxh0 ());

}

 

Char uart_put_char (char ch)

{

While (! (Utrstat0 & 0x2); // wait until thr is empty.

Wrutxh0 (CH );

Return ch;

}

When Mode 3 is used, the input and output functions can be used as follows:

Char uart_fifo_put_char (char ch)

{

While (ufstat0 & 0X4000 ));

Wrutxh0 (CH );

Return ch;

}

 

Char uart_fifo_get_char (void)

{

While (! (Ufstat0 & 0x1f ));

Eturn (char) (rdurxh0 ());

}