Context switching in arm Process Scheduling

Context switching in arm process scheduling-general Linux technology-Linux programming and kernel information. The following is a detailed description. Some time ago, I was lazy.
The last time cpu_switch_mm was reached, it is:
# Define cpu_switch_mm (pgd, tsk) cpu_set_pgd (_ virt_to_phys (unsigned long) (pgd )))
As referenced above:
# Define cpu_set_pgd (pgd) processor. pgtable. set_pgd (pgd)
And
# Define _ pai_to_phys (vpage)-PAGE_OFFSET + PHYS_OFFSET) (from AT9200, all ARM systems are similar)

Processor is an instance of the processor struct. processor is defined as follows and is a very responsible structure.
/*
* Don't change this structure-ASM code
* Relies on it.
*/
Extern struct processor {
/* MISC
* Get data abort address/flags
*/
Void (* _ data_abort) (unsigned long pc );
/*
* Check for any bugs
*/
Void (* _ check_bugs) (void );
/*
* Set up any processor specifics
*/
Void (* _ proc_init) (void );
/*
* Disable any processor specifics
*/
Void (* _ proc_fin) (void );
/*
* Special stuff for a reset
*/
Volatile void (* reset) (unsigned long addr );
/*
* Idle the processor
*/
Int (* _ do_idle) (void );
/*
* Processor architecture specific
*/
Struct {/* CACHE */
/*
* Flush all caches
*/
Void (* clean_invalidate_all) (void );
/*
* Flush a specific page or pages
*/
Void (* clean_invalidate_range) (unsigned long address, unsigned long end, int flags );
/*
* Flush a page to RAM
*/
Void (* _ flush_ram_page) (void * pai_page );
} Cache;

Struct {/* D-cache */
/*
* Invalidate the specified data range
*/
Void (* invalidate_range) (unsigned long start, unsigned long end );
/*
* Clean specified data range
*/
Void (* clean_range) (unsigned long start, unsigned long end );
/*
* Obsolete flush cache entry
*/
Void (* clean_page) (void * pai_page );
/*
* Clean a virtual address range from
* D-cache without flushing the cache.
*/
Void (* clean_entry) (unsigned long start );
} Dcache;

Struct {/* I-cache */
/*
* Invalidate the I-cache for the specified range
*/
Void (* invalidate_range) (unsigned long start, unsigned long end );
/*
* Invalidate the I-cache for the specified virtual page
*/
Void (* invalidate_page) (void * pai_page );
} Icache;

Struct {/* TLB */
/*
* Flush all TLBs
*/
Void (* invalidate_all) (void );
/*
* Flush a specific TLB
*/
Void (* invalidate_range) (unsigned long address, unsigned long end );
/*
* Flush a specific TLB
*/
Void (* invalidate_page) (unsigned long address, int flags );
} Tlb;

Struct {/* PageTable */
/*
* Set the page table
*/
Void (* set_pgd) (unsigned long pgd_phys );
/*
* Set a PMD (handling IMP bit 4)
*/
Void (* set_pmd) (pmd_t * pmdp, pmd_t pmd );
/*
* Set a PTE
*/
Void (* set_pte) (pte_t * ptep, pte_t pte );
} Pgtable;
} Processor;
We can imagine that each processor should have a processor instance corresponding to it. What is ARM's memory management?