CORTEX-A15 Memory Hierarchy

The ARM platform uses multiple levels of memory architecture to achieve speed and cost balance. For SoCs consisting of multicore CPUs, there is a set of caches inside each CPU, including: ICache, Dcache, and TLB. Multiple CPUs share a larger L2 cache.       The L2 cache interacts with the DDR3 memory outside the CPU. Both ICache and Dcache know the instruction cache and the data cache. The TLB is actually a cache of page tables within the CPU, and is also divided into L1 and L2, which are integrated within each CPU.



From for notes (Wiz)

CORTEX-A15 Memory Hierarchy