[Country EMBED strategy] [158] [SPI bare Metal Drive design]

SPI Controller Workflow

The SPI Controller provides 2 SPI interfaces. Each SPI interface has two channels, the TX channel and the RX channel, respectively. The CPU writes the data to the FIFO, writes the data to the Spi_tx_data register, so that the contents of this register are automatically moved to the sending FIFO, and if the CPU is going to read the data from the receiving FIFO, it accesses the register spi_rx_data, The data that receives the FIFO is then automatically moved to the Spi_rx_data register.

OK6410 SPI Bare-Metal program analysis

SPI initialization

U8 Spi_init () {

SPI Reset

Ch_cfg0 |= BIT5; SPI Soft Reset

Set Pin

Rgpccon &= ~0xffff;

Rgpccon |= 0x2222;

Configuring the CFG Register

Ch_cfg0 = 0b0111;

Configure MODE_CFG0

Mode_cfg0 = (63<<11);

Setting the Clock

clk_cfg0 = 100;

CLK_CFG) |= 1<<8;

return 0;

}

SPI Read/write

U32 spix_readwritedata (u32 txdata) {

do{

temp = (spi_stas0>>6) & 0x7F; Get the number of FIFO data sent

}whlie (Temp > 63); Send FIFO full, wait

SPI_TXDATA0 = TxData; Send data

do{

temp = (spi_stas0>>13) & 0x7F; Get the number of received data

}whlie (temp = = 0); Receive FIFO is empty, waiting for

return spi_rxdata0;

}

[Country EMBED strategy] [158] [SPI bare Metal Drive design]