Course Notes for assembly language programming 04-07

------ Drop: 4 lessons --------- Chapter 2: internal structure of 8086cpu
1. the microprocessor bus structure is divided into internal structure and external structure.
The 2.8086cpu chip has 40 pins, which are connected to the external logic for information exchange.
These pins are the microprocessor and bus. They have the following functions:
1. Exchange information with memory
2. Exchange information with IO devices through Io circuits. XX card.
3. Able to input and output signals
3. Bus: Address, control, and data bus;
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1. Address Bus: single item; the maximum accessible address space is related to the CPU address line
2. Data Bus: two-way; how much data can be transmitted, and can be exchanged with CPU, memory, or IO devices at a time

The number of digits of the data, that is, the bandwidth.
3. control bus: most of the individual items have some bidirectional
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The internal structure of the microprocessor: CPU
1. operation functions
2. Ability to receive and send data
3. A small amount of data can be saved internally: registers
4. operations that can store, decode, and execute commands
5. Provides the timing and control signals required by the entire system.
6. Respond to IO Device interruption requests

II. CPU Internal Structure
1. Controller: program counter, instruction register, instruction decoder, control logic component, stack indication

Consists of six parts.
2. Generator ALU
3. Io control logic
4. Working register: Address Register, data register

3.
1. program counter: used to save the next instruction address to be executed. It is also called the instruction address counter.
2. instruction register: Read the current instruction to be executed from the external register
3. instruction decoder: decode and analyze the preceding commands so that the CPU can know how to operate them.
4. control logic component: Send control signal: Cycle Pulse and potential transmission
5. processor-like Font: the current state of the temporary storage processor. Is the result positive or negative? Is it beneficial? Whether to enter

Signs such as whether the result is 0. Each bit represents a flag. We can test these records.

Status.
6. Stack indicator: address provided for Stack operations.

4. I/O control logic: function: input/output operations.

5. CPU program execution process:
1. Run Command 1, Run Command 2, Run Command 2, and run command 3 .... Low CPU Efficiency
To overcome these disadvantages:
8086 of commands are executed in parallel. The command queue is used.
--------- Biu Bus Interface Unit EU Execution Unit
Biu is responsible for reading the command to the queue, and waits until it knows it is full. EU is responsible for pulling the command from the queue, and the departure team

Column is empty.

======= 5th course ======= microprocessor's Register Organization ==============
I. This knowledge point is the key to learning assembly language programming.
There are 14 16-bit registers in 1.8086 and CPUs, which are used to provide operations, control command execution and

Addressing of commands and operands. Address, data, and control data.
Understanding the functions and usage of each register is the basis for learning assembly language programming.

2. Registers are divided into eight general-purpose registers, internal registers 5 = 4 + 1 pointer, and Alu mark registers = 16

.
14 registers can be divided into three categories based on their purposes: General Register 8, segment register 4, control register 2:

Pointer, flag

I. Eight General registers:
1. Four data registers:
2. Address pointer 2 and address change register 2 4

II. Four data registers are h-high and l-low. We can separate 8-bit high and 8-bit low storage.
AH Al ax -- Accumulators
Bh bl bx -- Base Address Register
Ch Cl CX -- counter: number of cycles
Dh dl dx -- data register
8-bit, 16-bit

If you want to store an 8-bit data during programming, you can select these 8 names to store

If you want to store a 16-bit data, you can use the four Register names to store the data.

3. Four address registers: Address pointer and address change register
SP -- Stack pointer register
BP -- base address pointer register
Si -- Source Address Register
Di -- Destination Address Register

Question:
In the continuous storage units below the memory address starting from 100 h, the-byte unoperator is stored.

Number binary number, calculate the sum of the 100 bytes (regardless of the benefit), and store the sum in Al?

Solution thinking:
Use the source address change register Si to point to the first address of the memory. The number of bytes to be accumulated is stored in the counter Cx.

The sum of all values is put into Al and the Al is cleared. Then, the SI is taken from the address unit.

The number of bytes is added to the original content of Al. The content of Si has been 1 and is cyclically executed for CX times.

MoV Si, 2000 h first address assignment
MoV CX, 100 cycles
MoV Al, 00 h cleared
Next: Add Al, [Si] use the content of Al as the number of additions, and use the content of Si as the address to locate the inner of this unit.

Adding (data) and Al, and saving them in Al.
INC Si // Si Value auto-increment 1
Loop next
// Note that the loop will automatically make the CX--1 as a loop counter.

================== 6th Course: ===== CPU Register Organization =========
I. Segment register
There are usually three types of information stored in the memory of the Microcomputer System:
Code -- indicates the operations performed by the CPU

Data-objects or results processed by a program

Stack information-saved return addresses and intermediate results

Code segment, data segment, and stack segment

CS code segment register, pointing to the current code segment, the instruction is taken out of this segment
DS data segment register, pointing to the current data segment.
Es additional data segment register.
SS points to the current stack segment

II. Two control registers
1. Instruction Pointer register IP: the offset address of the next memory to be executed
2. Flag: 9-bit useful
Status flag: Is 6 0? Overflow ?... Negative number? Carry?
Control flag: 3

============= 7th course ==============
I. Storage address space and data storage format
1. Memory Management, in bytes. One byte is 8 bits, and one bit is a binary

Bit
2. A total of 20 hop address bus, 2 (20) 1 MB addressable Space
3. Each byte corresponds to a unique address
4. The address range is 0-2 (20)-1.
5. Two consecutive bytes in the memory are defined as a word, with a low byte (8 bits)
6. In bytes, the maximum bit is 0, the maximum bit is 7, and the maximum bit is 15. Because the bitwise is from 0 subscript

So the highest digit is not 16, but 15.
7. variable name: Data Definition pseudocommand. Replace an address with a variable name. The address is hard to remember.

But we can use the corresponding address with the variable name.
8. DB byte DW word dd dubyte variable definition.
9. Even addresses are targeted; odd addresses are not targeted. Similar to the struct alignment problem.
1. Only one bus cycle is required for the command to access the word of an even address;
Two Bus cycles are required for accessing an odd address. Therefore, memory alignment can increase the access speed.
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II. Block Storage and physical address format
1. Why segment?
8086 there are 20 address lines, and the external storage space that can be addressable is 1 MB, and the internal storage can provide the address

There are 6 encoded address registers: bx bp cp dp... all are 16 bits, so use these 6 16 bits to send

The memory provides an external memory address, which can only provide 2 (16) 64 K addresses. Therefore, for 1 MB

Address addressing is not complete. The 16-bit address registers are:
BX
BP
Si
Di
SP
IP address these memories provide the memory with an in-segment offset address in some addressing mode.

To enable the external memory to be segmented, it is necessary to segment the external memory.
Divides an external 1 m space into several logical segments, thus expanding the addressing range to 1 MB.

2. How to segment?
In a 1 MB bucket, the time Encoding of each unit is called a physical address.
Divides 1 MB of storage space into several logical segments, with each segment at most 64kb
The starting address of each logical segment must be divided by 16, that is, is the low 4-bit binary of the starting address of a segment required?

Must be 0
Each segment has its own header, so remember the header address, so we can use the offset address to find something.
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