CPU Design-->verilog Understanding

1. The variables in the Verilog HDL language are only two categories of data types, wire and register Reg.
2. The network cable type represents the physical connection between Verilog HDL structured components, whose value is determined by the value of the source device that drives it, and the default value of the network cable is high impedance z if no drive source is connected to the network cable.
3. The register type represents an abstract data register, which can only be assigned in the always statement and the initial statement, and after the register variable is assigned, the value is preserved and will change only the next assignment. The default value of the register type variable is x, which is typically initialized in use.
4. The description of Verilog HDL language consists of two ways: Data flow description and behavior description. The data flow description method mainly uses the Assign statement to establish the connection between components. Thus the Assign statement is the "connection" statement. The behavior description mainly uses the always structure. In the Verilog HDL language, it is stated that each description statement is ";" End.
5. The way the modules are connected--and the module's structure allows multiple modules to be organized into larger modules. It is organized much like a function call with a shape parameter in C language. To illustrate the problem, we use the module to define the logic and, OR and XOR, and then construct the semi-additive using the method called by the module to illustrate the correlation between modules.

1Module BJQ (Input A,//define input Port a2 3Input B,//Define input Port B4 5Output Sum,//define and output port sum6 7Output Cout//Defining the Carry- out port cout8 9         ) ;Ten  OneWire s1,t1;//Defining connection Leads A  -Assign Cout =t1;//Carry Wire Connection -  theAssign Sum = S1;//Standard and wire connection -  -Yu Yu1 (A, B, T1);//Connection call logic and module -  +Yihuo Yihuo1 (A,B,S1);//Connection Invocation Logic XOR module -  +Endmodule

1Parameter mon=0, tue=1, wed=2, thu=3, fri=4, sat=5, sun=6;2 3reg [0:2] Day;4 5 integer Pocket_money;6 7  Case(Day)8 9tue:pocket_money=6;//Branch 1Ten  Onemon,wed:pocket_money=2;//Branch 2 A  -fri,sat,sun:pocket_money=7;//Branch 3 -  the default: pocket_money=0;//Branch 4 -  -Endcase

CPU Design-->verilog Understanding