Cpuid details _ reprint Baidu

Cpuid is an Intel Pentium command built into the upper-level CPU (CPU level 486 or lower is not supported), it is used to identify a type of CPU, it can return information such as the CPU level (family), model, CPU step (stepping ID), and CPU string. From this command, you can also obtain the CPU cache and TLB information.
The cpuid returned data type is defined in the eax register, while the value returned by the command is stored in the eax, EBX, ECx, and EDX registers.
The returned information is divided into two parts: basic information and extended information. when eax inputs the 0-3 parameter, it returns the basic CPU information. When eax inputs 0x8000000 to 0x800000x, it returns the extended function information of the CPU ). the extended information is only contained on the CPU of Pentium 4 and later. The CPU before Pentium 4 cannot obtain the extended information.

See the following table:
CPU-level basic information Scaling
486 or earlier CPU unavailable
Pentium 0x1 unavailable
Pentium Pro, Pentium 2 0x2 unavailable
Pentium 3 0x3 unavailable
Pentium 4 0*2 0x80000004
Xeon (Xeon) 0x2 0x80000004

If the input value is higher than the value of the processor, the cpuid command returns the return value of the maximum input value of the CPU (this sentence does not know how to say ),
For example, if 0x4 is input on Pentium 4, the CPU return value is the same as the return value of 0x2.

The following table describes the relationship between input values and return values:
Input value return value
-----------------------------------------------------------------
0x0 input value of the eax CPU Basic Parameter
EBX "genu"
ECX "Intel"
EdX "inEl"
------------------------------------------------------------------
0x1 eax CPU level, model and step
EBX has a lot of information, which is described below
ECX retention
Feature Information)

------------------------------------------------------------------
0x2 eax to edX all returned cache and TLB Information
------------------------------------------------------------------
0x3 eax Reserved
EBX retention
Ecx cpu serial number (0-31bit) (valid only in Pentium 3)
EdX CPU serial number (32-63bit) (valid only in Pentium 3)
------------------------------------------------------------------

0x80000000 maximum number of eax extended information inputs (CPU with extended information can return)
EBX retention
ECX retention
EdX retained
------------------------------------------------------------------
0x80000001 eax CPU features (signature) and extended feature bits)
EBX to ECx Reserved
------------------------------------------------------------------
0x80000002 eax processor string (processor brand string)
EBX processor string (continued)
ECX processor string (continued)
EdX processor string (continued)
------------------------------------------------------------------
0x80000003 eax processor string (continued)
EBX processor string (continued)
ECX processor string (continued)
EdX processor string (continued)
------------------------------------------------------------------
0x80000004 eax processor string (continued)
EBX processor string (continued)
ECX processor string (continued)
EdX processor string (continued)
------------------------------------------------------------------

When 0x1 is input, the return value of EBX is:
0th-7 bits: Brand Index)
8th-15 bits: clflush line size (clflush line size) (return value * 8 = cache line size)
16th-23 bits: Reserved
24th-31 bits: processor APIC physical ID (processor local APIC physical ID)

When 0x1 is input, the extended information returned by EDX is described as follows:

Bit label explanation
0 FPU floating point unit on-chip. Whether the CPU has built-in floating point computing units
1 VME virtual 8086 mode enhancements. Whether virtual 8086 mode is supported
2 de debugging extensions. Whether debugging is supported.
3 PSE page size extension. Whether pages larger than 4 MB are supported.
4 TSC time stamp counter. Whether the rdtsc command is supported. (Note: The rdtsc command can calculate the CPU frequency)
5 MSR module specific registers rdmsr and wrmsr instructions. Supported rdmsr and wrmsr (* Note 1)
6 PAE physical address extension. Whether physical addresses larger than 32bit are supported.
7 MCE machine check exception. (* Note 2)
8 cx8 cmpxchg8b instruction. Whether 8 bytes (64bit) Count comparison and switch commands are supported.
9 APIC On-Chip. Whether APIC (Advanced Programmable Interrupt Controller) is supported)
10 reserved
11 sep sysenter and sysexit instructions. Whether sysenter and sysexit commands are supported. (* Note 3)
12 mtrr memory type range registers. Whether MTTR is supported (* Note 4)
13 pge pte global BIT. Whether global page Directory Entry flag (global BIT in page Directory Entries) is supported)
14 MCA machine check architecture. Does the system support the MCA? The MCA is an error reporting mechanism for pentium4, Xeon, P6 Processors
15 cmov conditional move instructions. cmov command is available. (who can explain what cmov command is ?)
16 Pat page Attribute Table. Whether Pat is supported. Pat allows the operating system to specify 4 K Linear memory space
17 PSE-36 32-bit page size extension. Whether 4 GB of extended memory is supported
18 PSN processor serial number. Whether the processor serial number is supported. (P3 is valid)
19 clhcg clflush instruction. Whether clflush is supported. (* Note 5)
20 reserved
21 DS debug store. Whether debugging information can be written to the cache,
22. ACPI processor performance modulation registers. The processor uses special registers to allow software to control the operating cycle of the processor.
23 MMX inter MMX technology. Is MMX supported?
24 fxsr fxsave and fxrstor instructions. fxsave and fxrstor commands are available (* Note 6)
25 SSE. Whether SSE is supported.
26. Does sse2 support sse2.
27 ss self snoop. Whether the processor supports bus monitoring to prevent memory conflicts.
28 Reserved
29 TM thermal monitor. Does the CPU support temperature control.

30 & 31 Reserved
--------------------------------------------------------------
Note 1: rdmsr: Load MSR specified by ECx into edX: eax
Wrmsr: Write the value in edX: eax to MSR specified by ECx
NOTE 2:
The original Article is exception 18 is defined for machine checks, including cr4.mce for controlling the feature. this feature does not define themodel-specific implementations of machine-check error logging, reporting, andprocessor shutdowns. machine check exception handlers may have to depend onprocessor version to do model specific processing of the exception, or test for thepresence of the machine check feature.

NOTE 3: sysenter: fast call to privilege level 0 system procedures
Sysexit: fast return to privilege level 3 user code.

Note 4:
The original article is the mtrrcap MSR contains feature bits that describe what memory types are supported, how manyvariable mtrrs are supported, and whether fixed mtrrs are supported.

Note 5: clflush: flushes cache line containing m8.

Note 6: fxsave: Save the x87 FPU, MMX, XMM, and mxcsr register
Fxstor: Restore the x87 FPU, MMX, XMM, and mxcsr register

You can write a CPU check by yourself.ProgramNow;
# Include <stdio. h>

Void main ()
{
Unsigned long dbaseindex, dfeinfo, dfeinfo2, dcpubaseinfo;
Unsigned long dfeindex, dcpuexinfo, I;
Unsigned long dother [4], dtlb [4], dprocesn [2];
Char ccom [13];
Char cprostr [49];
Unsigned Int J;

_ ASM
{
XOR eax, eax
Cpuid
MoV dbaseindex, eax
MoV dword ptr ccom, EBX
MoV dword ptr ccom + 4, ECx // amd cpu should change ECx to edX
MoV dword ptr ccom + 8, EDX // amd cpu should change edX to ECx

MoV eax, 1
Cpuid
MoV dcpubaseinfo, eax
MoV dfeinfo, EBX
MoV dfeinfo2, EDX

MoV eax, 0x80000000
Cpuid
MoV dfeindex, eax

MoV eax, 0x80000001
Cpuid
MoV dcpuexinfo, eax

MoV eax, 0x80000002
Cpuid
MoV dword ptr cprostr, eax
MoV dword ptr cprostr + 4, EBX
MoV dword ptr cprostr + 8, ECx
MoV dword ptr cprostr + 12, EDX

MoV eax, 0x80000003
Cpuid
MoV dword ptr cprostr + 16, eax
MoV dword ptr cprostr + 20, EBX
MoV dword ptr cprostr + 24, ECx
MoV dword ptr cprostr + 28, EDX

MoV eax, 0x80000004
Cpuid
MoV dword ptr cprostr + 32, eax
MoV dword ptr cprostr + 36, EBX
MoV dword ptr cprostr + 40, ECx
MoV dword ptr cprostr + 44, EDX
}

If (dbaseindex> = 2)
{< br> _ ASM
{< br> mov eax, 2
cpuid
mov dtlb [0], eax
mov dtlb [2], EBX
mov dtlb [3], ECX
mov dtlb [4], EDX
}< BR >}< br> If (dbaseindex = 3)
{< br> _ ASM
{< br> mov eax, 3
cpuid
mov dprocesn [0], ECX
mov dprocesn [1], EDX
}< BR >}

ccom [12] = '\ 0'; // Add an ending character
printf ("CPU vendor: % s \ n", ccom );
printf ("CPU string: % s \ n", cprostr);
printf ("CPU basic parameter: Family: % x model: % x stepping ID: % x \ n ", (dcpubaseinfo & 0x0f00)> 8,
(dcpubaseinfo & 0xf0)> 4, dcpubaseinfo & 0xf );
printf ("CPU extension parameter: Family: % x model: % x stepping ID: % x \ n", (dcpuexinfo & 0x0f00)> 8,
(dcpuexinfo & 0xf0)> 4, dcpuexinfo & 0xf);

Printf ("CPU string index: 0x % x \ n", dfeinfo & 0xff );
Printf ("clflush wire size: 0x % x \ n", (dfeinfo & 0xff00)> 8 );
Printf ("processor APIC physical number: 0x % x \ n", (dfeinfo & 0xf000)> 24 );
If (dbaseindex> = 2)
{
Printf ("CPU cache & TLB information :");
For (j = 0; j <4; j ++)
{
If (! (Dtlb [J] & 0xff) printf ("%. 2x", dtlb [J] & 0xff );
If (! (Dtlb [J] & 0xff)> 8) printf ("%. 2x", (dtlb [J] & 0xff00)> 8 );
If (! (Dtlb [J] & 0xff0000)> 16) printf ("%. 2x", (dtlb [J] & 0xff0000)> 16 );
If (! (Dtlb [J] & 0xff000000)> 24) printf ("%. 2x", (dtlb [J] & 0xff000000)> 24 );
}
Printf ("\ n ");
}

If (dbaseindex = 3)
{
Printf ("CPU serial number: % x \ n", dprocesn [0], dprocesn [1]);
}
Printf ("FPU: % d \ t", dfeinfo2 & 0x00000001); // The following calls Code Too lazy to write ^
Printf ("VME: % d \ t", (dfeinfo2 & 0x00000002)> 1 );
Printf ("de: % d \ n", (dfeinfo2 & 0x00000004)> 2 );
Printf ("PSE: % d \ t", (dfeinfo2 & 0x00000008)> 3 );
Printf ("TSC: % d \ t", (dfeinfo2 & 0x00000010)> 4 );
Printf ("MSR: % d \ n", (dfeinfo2 & 0x00000020)> 5 );
Printf ("PAE: % d \ t", (dfeinfo2 & 0x00000040)> 6 );
Printf ("MCE: % d \ t", (dfeinfo2 & 0x00000080)> 7 );
Printf ("cx8: % d \ n", (dfeinfo2 & 0x00000100)> 8 );
Printf ("APIC: % d \ t", (dfeinfo2 & 0x00000200)> 9 );
Printf ("Sep: % d \ t", (dfeinfo2 & 0x00000800)> 11 );
Printf ("mtrr: % d \ n", (dfeinfo2 & 0x00001000)> 12 );
Printf ("PGE: % d \ t", (dfeinfo2 & 0x00002000)> 13 );
Printf ("MCA: % d \ t", (dfeinfo2 & 0x00004000)> 14 );
Printf ("cmov: % d \ n", (dfeinfo2 & 0x00008000)> 15 );
Printf ("Pat: % d \ t", (dfeinfo2 & 0x00010000)> 16 );
Printf ("PSE-36: % d \ t", (dfeinfo2 & 0x00020000)> 17 );
Printf ("PSN: % d \ n", (dfeinfo2 & 0x00040000)> 18 );
Printf ("clfsn: % d \ t", (dfeinfo2 & 0x00080000)> 19 );
Printf ("ds: % d \ t", (dfeinfo2 & 0x00200000)> 21 );
Printf ("ACPI: % d \ n", (dfeinfo2 & 0x00400000)> 22 );
Printf ("MMX: % d \ t", (dfeinfo2 & 0x00800000)> 23 );
Printf ("fxsr: % d \ t", (dfeinfo2 & 0x01000000)> 24 );
Printf ("SSE: % d \ n", (dfeinfo2 & 0x02000000)> 25 );
Printf ("sse2: % d \ t", (dfeinfo2 & 0x04000000)> 26 );
Printf ("SS: % d \ t", (dfeinfo2 & 0x08000000)> 27 );
Printf ("TM: % d \ n", (dfeinfo2 & 0x20000000)> 29 );

Printf ("\ n Other information: \ n ");
Printf ("---------------------------------------- \ n ");
Printf ("in \ t \ teax \ t \ tebx \ t \ tecx \ t \ TEDx ");
For (I = 0x80000004; I <= dfeindex; ++ I)
{
Dother [0] = dother [1] = dother [2] = dother [3] = 0;
_ ASM
{
MoV eax, I
Cpuid
MoV dother [0], eax
MoV dother [1], EBX
MoV dother [2], ECx
MoV dother [3], EDX
}
Printf ("\ n0x %. 8x \ t0x %. 8x \ t0x %. 8x \ t0x %. 8x \ t0x %. 8x ", I, dother [0], dother [1], dother [2], dother [3]);
}
Printf ("\ n ");
System ("pause ");
}

TLB and cache details:
0x00 null Descriptor
0x01 instruction TLB: 4k-byte pages, 4-way set associative, 32 entries
0x02 instruction TLB: 4m-byte pages, 4-way set associative, 2 entries
0x03 data TLB: 4k-byte pages, 4-way set associative, 64 entries
0x04 data TLB: 4m-byte pages, 4-way set associative, 8 entries
0x06 1st-Level Instruction Cache: 8 K bytes, 4-way set associative, 32 byte line size
0x08 1st-Level Instruction Cache: 16 K bytes, 4-way set associative, 32 byte line size
0x0a 1st-Level data cache: 8 K bytes, 2-way set associative, 32 byte line size
0x0c 1st-Level data cache: 16 K bytes, 4-way set associative, 32 byte line size
0x22 3rd-level cache: 512 K bytes, 4-way set associative, 64 byte line size
0x23 3rd-level cache: 1 M bytes, 8-way set associative, 64 byte line size
0x25 3rd-level cache: 2 M bytes, 8-way set associative, 64 byte line size
0x29 3rd-level cache: 4 M bytes, 8-way set associative, 64 byte line size
0x40 No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level Cache
0x41 2nd-level cache: 128 K bytes, 4-way set associative, 32 byte line size
0x42 2nd-level cache: 256 K bytes, 4-way set associative, 32 byte line size
0x43 2nd-level cache: 512 K bytes, 4-way set associative, 32 byte line size
0x44 2nd-level cache: 1 M byte, 4-way set associative, 32 byte line size
0x45 2nd-level cache: 2 M byte, 4-way set associative, 32 byte line size
0x50 instruction TLB: 4-kbyte and 2-mbyte or 4-mbyte pages, 64 entries
0x51 instruction TLB: 4-kbyte and 2-mbyte or 4-mbyte pages, 128 entries
0x52 instruction TLB: 4-kbyte and 2-mbyte or 4-mbyte pages, 256 entries
0x5b data TLB: 4-kbyte and 4-mbyte pages, 64 entries
0x5c data TLB: 4-kbyte and 4-mbyte pages, 128 entries
0x5d data TLB: 4-kbyte and 4-mbyte pages, 256 entries
0x66 1st-Level data cache: 8 KB, 4-way set associative, 64 byte line size
0x67 1st-Level data cache: 16 KB, 4-way set associative, 64 byte line size
0x68 1st-Level data cache: 32kb, 4-way set associative, 64 byte line size
0x70 Trace Cache: 12 k-μ op, 8-way set associative
0x71 Trace Cache: 16 K-μ op, 8-way set associative
0x72 Trace Cache: 32 K-μ op, 8-way set associative
0x79 2nd-level cache: 128kb, 8-way set associative, sectored, 64 byte line size
0x7a 2nd-level cache: 256kb, 8-way set associative, sectored, 64 byte line size
0x7b 2nd-level cache: 512kb, 8-way set associative, sectored, 64 byte line size
0x7c 2nd-level cache: 1 MB, 8-way set associative, sectored, 64 byte line size
0x82 2nd-level cache: 256 K bytes, 8-way set associative, 32 byte line size
0x84 2nd-level cache: 1 M byte, 8-way set associative, 32 byte line size
0x85 2nd-level cache: 2 M byte, 8-way set associative, 32 byte line size

For example, a CPU executes
MoV eax, 2
Cpuid
After,
The return value is as follows:
Eax 0x665b5001
EBX 0x0
ECX 0x0
EdX 0x007a7000
The CPU cache information is:
1. 0x66: 1st-Level data cache: 8kb, 4-way set associative, 64 byte line size
2. 0x5b: Data TLB: 4-kbyte and 4-mbyte pages, 64 entries
3. 0x50: instruction TLB: 4-kbyte and 2-mbyte or 4-mbyte pages, 64 entries
4. 0x01: instruction TLB: 4k-byte pages, 4-way set associative, 32 entries
5. 0x7a: 2nd-level cache: 256kb, 8-way set associative, sectored, 64 byte line size
6. 0x70: Trace Cache: 12 k-μ op, 8-way set associative

Detailed description of the CPU string index (Brand Index:
0x0: the CPU does not support Brand Index.
0x1: celeon CPU
0x2: Pentium 3
0x3: Pentium 3 Xeon
0x4-0x7: unused
0x8: Pentium 4

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