Create a project in Vivado and build a zynq embedded system

Open Vivado, click Create New Project,

Below the establishment sub-directory project must tick. Click Next:

Select the first one, and the options below are not checked. Click Next:

Select Verilog language, do not add files, and then always click Next: To the selection of the board step, directly click on the boards,
Choose

Complete.

To create a zynq embedded system:

Create a block design, expand IP Integrator in the Flow Navigator area, select Create Block design

The workspace will then open the chart canvas for the IP integrator, and we'll build our own system in a blank area like painting. The smallest unit of operation here is the IP core, the free IP core provided by Xilinx can be added directly, and the user can also customize the IP core.

Right-click on the Add IP on the blank board, enter ZYNQ in Search, double-click ZYNQ7 Processing System to add PS end to IP core canvas in the results.

In TCL console we will see the following information:

In fact, the graphical interface of the operation, will be converted to TCL command execution.
To make the PS module work in Zedboard, also configure it, double-click PS

Click Presets, Zedboard, using the default configuration provided by Vivado for Zedboard, click OK

Click on the DDR interface, right when the pen appears, choose Make External, Fixed_io use the same method.

Add the Axi GPIO Ipcore to the system below. , right click on the empty space to add the IP core, the search bar input GPIO, double click on Axi GPIO add complete.

Then click Run Connection Automation Select/axi_gpio_o/s_axi, click OK to have two new IP cores added automatically.

Then click Run Connection Automation,select Board interface under Select Leds_8bits.
This completes the basic configuration, and IP integrator automatically assigns the address space to the logical devices on the Axi bus so that the arm can be addressed to the device.

Allocate 64k address space for Axi Gpio, base site is 0x41200000, save project. On the left side of the Diagram window toolbar, select the Validate Dsign button to check the design validity.

So far, the IP subsystem has been designed and completed!!! Below we will design complete block dsign to generate a comprehensive HDL design file.
In the Sources window, right-click zynq_system_1 Select Generate Output Products

Click Generate to generate a constraint file for the HDL source file and the appropriate port. Then right-click Zynq_system_1, select Create HDL wrapper selection, click OK. Here Vivado generates a top-level file for the IP subsystem, allowing us to synthesize, implement, and generate bitstream for the system.
In flow Navigator, expand Program and Debug, and click Generate Bitstream. Click OK

This process will last for a long time, and when finished, a dialog box will pop up, choosing open implementation Design

The design is imported into the SDK, then the arm can be programmed to control the Zedboard led light.
Expand IP Integrator and click Open Block Design to select the pop-up zynq_system_1.bd
Executes the File->export->export hardware for SDK command, which pops up a dialog box to make sure that the Check button is selected.
The next blog will be programmed in the SDK to do the small lights! This blog is over! ~ ~ ~ Very tired!

Create a project in Vivado and build a zynq embedded system