Decided to analyze u-boot-1.1.4 source code from scratch (1)

I have read a lot of articles about U-boot on the Internet, and some of them are also detailed, but it is always a little problem that I have transplanted to my 2410 Development Board according to the above steps, so I decided to analyze the source code of the u-boot-1.1.4 from the beginning, hope to have a deep understanding of U-boot, and finally transplanted to my Development Board. this requires a bit of compilation and C basics. I wrote the minimum startup code on MySQL 2410. I believe this is not a big problem. the following is from the code entry address u-boot-1.1.4 \ CPU \ ARM920T \ Start. start analysis at S :. globl _ start
_ Start: B Reset
Ldr pc, _ undefined_instruction
Ldr pc, _ software_interrupt
Ldr pc, _ prefetch_abort
Ldr pc, _ data_abort
Ldr pc, _ not_used
Ldr pc, _ IRQ
Ldr pc, _ fiq_undefined_instruction:. Word undefined_instruction
_ Software_interrupt:. Word software_interrupt
_ Prefetch_abort:. Word prefetch_abort
_ Data_abort:. Word data_abort
_ Not_used:. Word not_used
_ IRQ:. Word IRQ
_ FIQ :. word FIQ. balignl 16, 0xdeadbeef Note :. globl is equivalent to global in ads ,. word is equivalent to DCD in ads, which refers to the memory unit for allocating a word. Its value is undefined_instruction ,. balignl should be equivalent to align (the align directive aligns the current location to a specified boundary by padding with zeroes.) In ads .), it indicates that the current position is in a certain format by filling in 0. then the program jumps to the reset to start executing: Reset:
Mrs r0, CPSR
Bic r0, R0, # 0x1f
ORR r0, R0, #0xd3/* blocks IRQ interruptions, FIQ interruptions, and enters the management mode */
Msr cpsr, R0 # If defined (config_s3c2400)
# Define pwtcon 0x15300000
# Define intmsk 0x14400008
# Define clkdivn 0x14800014
# Elif defined (config_s3c2410)
# Define pwtcon 0x53000000/* define the relevant register address, because get 2410addr. Inc is not used here, So define it by yourself */
# Define intmsk 0x4a000008
# Define intsubmsk 0x4a00001c
# Define clkdivn 0x4c000014
# Endif # If defined (config_s3c2400) | defined (config_s3c2410)
LDR r0, = pwtcon/* disable the watchdog */
MoV R1, #0x0
STR R1, [R0] mov R1, #0 xffffffff/* shield all interrupts */
LDR r0, = intmsk
STR R1, [R0]
# If defined (config_s3c2410)
LDR R1, = 0x3ff/* shield all sub-interrupts */
LDR r0, = intsubmsk
STR R1, [R0]
# Endifldr r0, = clkdivn/* Set fclk: hclk: pclk = */
MoV R1, #3
STR R1, [R0]
# Endif/* config_s3c2400 | config_s3c2410 */# ifndef config_skip_lowlevel_init
BL cpu_init_crit
# Endif jump to the cpu_init-crit, the Code is as follows cpu_init_crit: mov r0, #0
MCR P15, 0, R0, C7, C7, 0/* flush V3/v4 cache */
MCR P15, 0, R0, C8, C7, 0/* flush V4 TLB */SET related control registers such as cache and MMU, its definition can be found on page 1.2 of S3C2410X User's Manual 546, where bit13 is V bit: base location of exception registers, 0 = low addresses = 0x0000 bytes, 1 = high addresses = 0 xFFFF 0000, B bit is big-Endian/little-Endian, bit1 is alignment fault enable, bit12 is I bit, instruction
Cache enable.
MRC P15, 0, R0, C1, C0, 0
Bic r0, R0, #0x00002300 @ clear bits 13, 9: 8 (-- V--- RS)
Bic r0, R0, #0x00000087 @ clear bits 7, 2: 0 (B ----cam)
ORR r0, R0, #0x00000002 @ set bit 2 (a) Align
ORR r0, R0, #0x00001000 @ set bit 12 (I) I-Cache
MCR P15, 0, R0, C1, C0, 0, then save the PC address and jump to lowlevel_init to initialize the memory control register. The LR here is the PC address before entering cpu_init_crit and needs to be saved, and so on.

MoV IP, LR
BL lowlevel_init
MoV LR, IP
MoV PC, LR then enters lowlevel_init, where a loop is executed, equivalent to 13 cycles, assigning a pre-defined Table value to 13 consecutive Registers starting from bwscon. these registers define the bank1-bank7 control settings, including the initialization of SDRAM. The Code is as follows: lowlevel_init: LDR r0, = smrdata/* The LDR here is a direct address jump, non-location-independent code, so the smrdata here is the connection address, that is, above 0x33f80000 */
LDR R1, _ text_base/* defines text_base = 0x33f80000 */In the u-boot-1.1.4 \ board \ smdk2410 \ congfig. mk */
Sub r0, R0, R1/* In fact, if the preceding LDR command uses the ADR command code, this line does not need to be used */
LDR R1, = bwscon/* bus width status controller */
Add R2, R0, #13*4
0:
LDR R3, [R0], #4
STR R3, [R1], #4
CMP R2, R0
BNE 0b/* everything is fine now */
MoV PC, LR. ltorg
/* The literal pools origin */smrdata:
. Word (0 + (bda-bwscon <4) + (b2_bwscon <8) + (b3_bwscon <12) + (b4_bwscon <16) + (b5_bwscon <20) + (b6_bwscon <24) + (b7_bwscon <28 ))
. Word (b0_tacs <13) + (b0_tcos <11) + (b0_tacc <8) + (b0_tcoh <6) + (b0_tah <4) + (b0_tacp <2) + (b0_pmc ))
. Word (b1_tacs <13) + (b1_tcos <11) + (b1_tacc <8) + (b1_tcoh <6) + (b1_tah <4) + (bw.tacp <2) + (bw.pmc ))
. Word (b2_tacs <13) + (b2_tcos <11) + (b2_tacc <8) + (b2_tcoh <6) + (b2_tah <4) + (b2_tacp <2) + (b2_pmc ))
. Word (b3_tacs <13) + (b3_tcos <11) + (b3_tacc <8) + (b3_tcoh <6) + (b3_tah <4) + (b3_tacp <2) + (b3_pmc ))
. Word (b4_tacs <13) + (b4_tcos <11) + (b4_tacc <8) + (b4_tcoh <6) + (b4_tah <4) + (b4_tacp <2) + (b4_pmc ))
. Word (b5_tacs <13) + (b5_tcos <11) + (b5_tacc <8) + (b5_tcoh <6) + (b5_tah <4) + (b5_tacp <2) + (b5_pmc ))
. Word (b6_mt <15) + (b6_trcd <2) + (b6_scan ))
. Word (b7_mt <15) + (b7_trcd <2) + (b7_scan ))
. Word (refen <23) + (trefmd <22) + (Trp <20) + (TRC <18) + (TCHR <16) + refcnt)
. Word 0x32/* some parameters are incorrect here. You need to set them according to the actual parameters of the Board, although sometimes it works normally */
. Word 0x30
. Word 0x30 after execution, the program returns to the next line of cpu_init_crit to start execution. The Code is as follows: # ifndef config_skip_relocate_uboot
Relocate:/* relocate U-boot to Ram */
ADR r0, _ start/* _ start is the starting address of the current Code, that is, the starting address of Rom 0 */
LDR R1, _ text_base/* _ text_base is the connection start address of the code segment */
CMP r0, R1/* if the two are equal, they are already running in Ram and do not need to be copied */
Beq stack_setupldr R2, _ armboot_start/* _ armboot_start is defined as _ armboot_start :. word _ start indicates that the value remains unchanged during running, while _ start indicates that it is different from running in Ram */
LDR R3, _ bss_start/* here is a little complicated, but I may have seen it n times, so I will not analyze it here */
Sub R2, R3, R2/* R2 <-size of armboot */
Add R2, R0, R2/* R2 <-source end address */copy_loop:
Ldmia R0 !, {R3-r10}/* copy from Source Address [R0] */
Stmia R1 !, {R3-r10}/* Copy to target address [R1] */
CMP r0, R2/* Until source end addreee [R2] */
Ble copy_loop
# Endif/* config_skip_relocate_uboot */stack initialization: stack_setup:
LDR r0, _ text_base
Sub r0, R0, # maid/* malloc area */
Sub r0, R0, # cfg_gbl_data_size/* bdinfo */
# Ifdef config_use_irq
Sub r0, R0, # (config_stacksize_irq + config_stacksize_fiq)
# Endif
Sub sp, R0, #12/* Leave 3 words for abort-stack */clear_bss:/* clears the BSS segments from _ bss_start to _ bss_end */
LDR r0, _ bss_start
LDR R1, _ bss_end
MoV R2, #0x00000000 clbss_l: Str R2, [R0]
Add r0, R0, #4
CMP r0, r1
Ble clbss_l becomes more and more complex. In the beginning, we were particularly confused about the memory distribution of U-boot in Ram. From here we can see that: _ text_base 0x33f80000 malloc area 0x33f80000-1__malloc_len bdinfo slave stack crashes here, the start code of the assembly part ends. by executing the following long jump command, you can jump to Ram and execute part of the C language code. The LDR pseudo command is location-related, that is, the address when you jump to the connection. ldr pc, _ start_armboot_start_armboot :. word start_armboot