Decoupling, bypass capacitance

The so-called decoupling, that is, to prevent the front and back circuit network current size changes, in the power supply circuit formed by the current impact on the normal work of the network. In other words, the decoupling circuit can effectively eliminate the parasitic coupling between the circuit networks.

Selection of decoupling capacitors
Masters and predecessors always tell us the rule of thumb: "Place on the power access side of the board
A 1~10μf capacitor that filters out low-frequency noise, and a power-to-ground between each device on the board
A 0.01~0.1μf capacitor to filter out high-frequency noise. "Most of the high-speed PCB designs that are available in bookstores
, high-speed digital circuit design in the classic tutorial also do not bother to cite the preferred law (the foreigner commonly known as rule of
THUMB). But why use it like this? You crossing, if you are an expert in circuit design, you can do it.
Something more important, because the following content is only for me, such as entry-level or even door-level novice.
Do the circuit people know the need to put some small capacitance near the chip, as to how big? How much do you put? How
You put it? The issue of the elimination of the article many, but relatively scattered in some of the predecessors of the masterpiece. My humble
Try to use the merely method to put a few questions together, hoping to deepen the understanding of the problem;
Unfortunately, these are very helpful to your study and work, and I am honored to have a good fart.
First of all, I would like to introduce two common simple concepts.
What is a bypass? Bypass (Bypass), which is to give some harmful parts of the signal to provide a low
The path of the impedance. High frequency interference in the power supply is a typical useless ingredient that needs to be advanced before it enters the target chip.
Kill, generally we use the capacitor to achieve this purpose. The capacitance used for this purpose is the so-called bypass capacitor
(Bypass capacitor), which utilizes the frequency impedance characteristics of the capacitor (the frequency characteristics of the ideal capacitor with the frequency
increase, impedance reduction, as the earth knows), it can be seen that the bypass capacitor is mainly for high-frequency interference (high is
In contrast, it is generally believed that above 20MHz is high frequency interference, and below 20MHz is low frequency ripple.
What is decoupling? Decoupling (decouple), the earliest used in multistage circuits, to ensure the transmission between the pre-
The measures taken to pass the signal without affecting the static working point of each level. Decoupling in the power supply means that when the chip is in
When the switch action or output changes, it is necessary to extract the large current from the power line, the instantaneous large
Current can cause a decrease in voltage on the power line, causing interference with itself and other devices. To reduce this
A "small pool" of electricity stored near the chip to provide this instantaneous high-current capability.
In power circuits, both bypass and decoupling are designed to reduce power supply noise. The bypass is mainly to reduce the power
The noise on the source interferes with the device itself (self-protection) and the decoupling is designed to reduce the noise generated by the device
Interference (not in the skeleton). Some people say that decoupling is for low frequency, bypass is for high frequency, I think this is
Inaccurate, the high-speed chip internal switch operation may be up to the upper GHz, resulting in interference with the power cord has been significantly
Does not belong to the low frequency range, for this purpose the decoupling capacitor also needs to have very good high-frequency characteristics. This article discusses the following
Decoupling and bypass are not deliberately differentiated, and are thought to filter out noise regardless of the source of the noise.
After a brief explanation of the bypass and decoupling, let's look at how the chip works on the power cord.
interfere with. We set up a simple IO buffer model with the output using the totem pole IO drive circuit, which consists of two interconnected
The output stage consisting of a complement MOS tube drives a transmission line with a matching resistor at the serial source end (transmission line impedance is Z0).
In order to make a pure document format, as far as possible to use the text description, do not use pictures, so as to understand the band
To a certain difficulty, the crossing laughed at. The sum of the package inductance and lead inductance of the supply pin and the ground pin
For: LV and LG. Two complementary MOS tubes (grounded nMOS and PMOs) are simply used as switches. False
The voltage and current at each point of the transmission line at the initial moment are zero, and in a moment the device will drive the transmission line to a high power
The device is required to absorb current from the power supply pins. In time T1, make PMOs tube conduction, current from PCB board
The VCC flows through the encapsulated inductor LV, crosses the PMOs tube, series the terminating resistor, and then flows into the transmission line, the output
The current amplitude is vcc/(2xz0). Current continues a complete return on the Transmission line Network (round-trip)
Time, at the end of the time T2. After the entire transmission line is charged, there is no need for additional incoming current to dimension
Hold. When the current surges through the encapsulated inductance LV, the power supply point inside the chip generates a voltage that is pulled low
Move. The disturbance is called the synchronous switching noise in the power supply (ssn,simultaneous switching Noise;
Sso,simultaneous switching Output Noise) or Delta I noise.
In time T3, close the PMOs tube, this action will not lead to the generation of impulse noise, because in this
The front PMOs tube is open and no current flows. At the same time open the nMOS tube, then the transmission line, ground level
The inductor LG and the nMOS tube form a circuit, with instantaneous current flowing through the switch B, so that the ground inside the chip
A disturbance at the junction where the reference level point is raised. The disturbance is called ground-bounce noise in the power supply system.
(Ground Bounce, I personally read the ground tan).
There is a certain inductance in the actual power system, such as chip pin, PCB trace, power layer and bottom layer.
Value, so the SSN and ground-bounce noise on IC-level analysis is board
exist, not just inside the chip. For the entire power distribution system (Power distribute
System), this is called the power supply voltage collapse noise. Because of the switching operation of the chip output and the chip
Internal operation, the need for instantaneous extraction of large current from the power supply, and the power characteristics can not be fast response to the power
The switching frequency of the high-speed switching power supply is only a MHz magnitude. To ensure that the voltage on the power cord near the chip is not
Because SSN and ground-bounce noise are reduced by more than the tolerances specified in the device manual, this requires a high-speed
The flow demand provides a storage capacitor, which is the decoupling capacitor we want.
If the capacitor is the ideal capacitor, the larger the capacitor, the better, because the larger the capacitance,
The stronger the instantaneous power supply, the lower the value of the resulting rail collapse, the more stable the voltage value. But
, the actual capacitance is not the ideal device, because of material, packaging and other aspects of the impact, with inductance, resistance, etc.
Additional characteristics, especially in the high-frequency environment, more like the electrical characteristics of the inductor. We all know the actual capacitance
Model is simply built with capacitance, resistance and inductance. In addition to capacitance C, the following parasitic parameters are included:
1. Equivalent series resistance ESR (RESR): the equivalent series resistance of a capacitor is the pin resistor of the capacitor
In series with the equivalent resistance of two plates of the capacitor. When there is a large AC current passing through the capacitor, the RESR makes the capacitor
Energy consumption (resulting in loss), which is commonly used in capacitors to represent this parameter.
2. Equivalent series inductance ESL (LESL): the equivalent series inductance of the capacitor is the pin inductance of the capacitor
In series with the equivalent inductance of the capacitor two plates.
3, equivalent shunt resistance EPR Rp: is what we commonly call the capacitor leakage resistance, in AC-coupled
Applications, storage applications (such as analog integrators and sample-holding), and when capacitors are used in high impedance circuits, the RP is
An important parameter, the charge in the ideal capacitor should only change with the external current. The RP in the actual capacitor, however, makes
The charge is released slowly at a speed determined by the RC time constant.
Or two parameters RDA, CDA is also the capacitance distribution parameters, but in the actual should affect the comparison
Small, it will save the bar. So there are three important parameters of capacitance distribution: ESR, ESL, EPR. The most important of these is
ESR, ESL, in the actual analysis of the capacitance model is usually only the RLC simplified model, that is, the analysis of capacitance C, ESR
Esl. Because of the influence of parasitic parameters, especially the effect of ESL, the frequency characteristics of the actual capacitance exhibit impedance and
The frequency is "V" curve, the low frequency with the increase in frequency, capacitance impedance reduction; When the lowest point, the capacitance
The impedance is equal to ESR, and the impedance increases with increasing frequency, showing inductance characteristics (thanks to ESL). So
The choice of capacitance is not only about the capacitance, but also the other factors that need to be considered. Including:
1, capacitance capacity, 2, dielectric material, 3, the capacitance of the geometric size and placement position.
All of the starting points to consider are to reduce the inductance between the power supply ground (to meet the maximum capacitance resistance
When there is a large instantaneous current flowing through the power supply system, it is not necessary to produce a large noise interference chip
Pin. There are two common ways to calculate the required capacitance:
Simple method: The size of the decoupling capacitor is calculated by the output-driven change;
Complex method: Calculates the size of the decoupling capacitor by the maximum inductance allowed by the power supply system.
We assume that a model, in a vcc=3.3v SRAM system, has 36 output data lines,
The load on the single data line is CLOAD=30PF (quite large), and the output driver needs to be in Tr=2ns (rising
Load from 0V to 3.3V, the required supply voltage requirement in the chip data is 3.3v+0.3v/-
0.165V.

The Brexit capacitor is used to store energy.Bypassis to prevent the power supply from being pulled low to affect the chip,Back to Europeis to prevent the switching pulses of the chip from affecting the power supply or peripheral circuitry

Decoupling, bypass capacitance