Deep understanding of ARM architecture (cloud6410)-source code example of cloudmonitor

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When the system operation is subject to external interference or system errors, the program sometimes runs and crashes the entire system. It will set a period of time when it exceeds this period of time, jump out of the program and enter the interrupt processing program. Watchdog is essentially a timer, so it should also have the features of a common timer. Yes, it will also cause an event when the timer times out, this event can be either a system interruption or a system restart signal (reset signal ). In this case, the timer that can send the system restart signal is called watchdog. We don't want to see the watchdog timer interruption, so we have to try to avoid it. The main method is to assign a value to the register of the watchdog timer before the interrupt occurs, so that its timer starts to record. This method is commonly known as dog Feed.

The following describes the functions of the watchdog timer:

As a regular clock and can interrupt

When used as a watchdog timer, when the clock Counter is reduced to zero, it will generate a reset signal.

The processor watchdog timer is used to resume the Controller operation wheneverit is disturbed by malfunctions such as noise and system errors. The watchdogtimer
Generates the reset signal.

It can be usedas a normal 16-bit interval timer to request interrupt service. advantagein using wdt instead
Of PWM timer is that wdt generates the reset signal.


The watchdogtimer provided des the following features:

• Normal interval Timer mode with interruptrequest.

• Internal reset signal is activated when thetimer Count value reaches 0 (time-out ).

• Level-triggered interrupt mechanic.

The watchdog module includes an 8-bit pre-divider, a divider, and a 16-bit counter. Its 8-bit pre-divider divides pclk into four frequencies: 16, 32, 64, and 128. Watchdog can select the frequency at which it works. S3C2440 uses three registers to operate the watchdog:

Watchdog timer control register (wtcon)

Watchdog timer data register (wtdat)

Watchdog timer count register (wtcnt)

Figure 34-1shows the functional block diency of the watchdog timer. The Watchdog timeruses only pclk as its source clock. The pclk frequency is prescaled to generatethe corresponding
Watchdog timer clock, and the resulting frequency is dividedagain.

The prescalervalue and the frequency division factor are specified in the watchdog timercontrol (wtcon) Register. Valid prescaler values range from 0 to 28-1. thefrequency Division
Factor can be selected as 16, 32, 64, or 128.

Use thefollowing equation to calculate the watchdog timer clock frequency and theduration of each timer clock cycle:

T_watchdog = 1/(pclk/(prescaler value + 1)/division_factor)



1. Once the watchdog timer is enabled, the value ofwatchdog timer data (wtdat) Register cannot be automatically reloaded into thetimer counter (wtcnt). For this reason, an initial value must
Be written to thewatchdog timer count (wtcnt) Register, before the watchdog timer starts.

2. When the 89c6410 is in debug mode using embeddedice, the watchdog timer must not operate. The watchdog timer can determinewhether or not it is currently in the debug mode from the CPU coresignal (dbgack
Signal). Once the dbgack signal is asserted, the reset output ofthe watchdog timer is not activated as the watchdog timer is expired.


Watchdog register ing:

1. watchdog timer control (wtcon) Register

Wtcon allows the user to enable the watchdog timer and select the clock from different four sources, enable the interruption, and enable the watchdog timer output. The watchdog timer is used to reset the system after a system failure. If you do not want to reset, the Enable timer is invalid.

The wtconregister allows the user to enable/disable the watchdog timer, select the clocksignal from 4 different sources, enable/disable interrupts, and enable/disablethe Watchdog
Timer output.

The watchdogtimer is used to resume the initi6410 restart on mal-function after its power on. At this time, disable the interrupt generation and enable the watchdog timeroutput
For reset signal.

If controllerrestart is not desired and if the user wants to use the normal timer only, which is provided by the watchdog timer, enable the interrupt generation anddisable
Watchdog timer output for reset signal.

Note: initial state of 'reset enable/disable' is 1 (reset enable ). if user do notdisable this bit, initi6410 will be rebooted in about 5.63sec (in the case ofpclk is 12 MHz ). so at boot loader,
This bit shoshould be disabled before underControl of operating system, or firmware.


2. watchdog timer data (wtdat) Register

Wtdat is used to determine the timeout period. The content of wtdat cannot be automatically loaded into the timer count during the initial timer operation. However, using 0x8000 will drive the first timeout. In this case, the value of wtdat will be automatically loaded into wtcnt.

The wtdatregister is used to specify the time-out duration. The content of wtdat cannotbe automatically loaded into the timer counter at initial watchdog timeroperation. However,
Using 0x8000 (Initial Value of wtcnt) will drive the firsttime-out. Then, the value of wtdat will be automatically reloaded into wtcnt.

3. watchdog timer count (wtcnt) Register

The wtcnt register contains the current count values for the watchdogtimer during normal operation.

Note: The content of the wtdat register cannot be automatically loaded into thetimer count register when the watchdog timer is enabled initially, so the wtcntregister must be
Set to an initial value before enabling it.

Definition register:

//watchdog#define WTCON    (*(volatile unsigned *)(0x7E004000))#define WTDAT    (*(volatile unsigned *)(0x7E004004))#define WTCNT    (*(volatile unsigned *)(0x7E004008))

Initialization function:

Void init_watchdog () {wtdat = 0xff; wtcnt = 0x8000; wtcon = 0xc021; // The prescaler value is 6 to 16}

Call in the mian function:


Note: The program is downloaded to the memory and run through the friendly superboot. The system is reset about 2 seconds later, and pclk = 133 m.


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