Deep understanding of ARM architecture (cloud6410)-UART instances

This series of articles written by muge0913, reproduced please note the Source: http://blog.csdn.net/muge0913/article/details/7393199

Author: Zhang tonghao, mail: muge0913@sina.com

1. Summary Overview

Each of the four independent asynchronous serial ports can work in the interrupt mode or DMA mode. That is to say, UART can generate an interrupt or DMA request. UART can provide up to 3 Mbps. Each UART contains two 64-bit FIFO queues for receiving and sending buffering respectively.

The UART includes programmable baud rate, infrared transmitting and receiving, one or two stop parity bits, bits, and parity checks. Each UART contains a baud rate generator, receiving and sending control unit.

The baud rate can be locked by pclk, ext_uclk0, or ex_uclk1. The sending receiver contains a 64-bit FIFO and a data transmitter respectively. By writing data to the first-in-first-out (FIFO) instance, the data in the first-in-first-out (FIFO) instance is copied to the data er and sent out through the txdn pin. Opposite to receiving data: rxdn-> datashifter-> FIFO.

2. Features features

Rxd0, txd0, rxd1, txd1, rxd2, txd2, rxd3and txd3 support DMA and interrupt formats.

UART 0, 1, 2, and 3 support infrared communication and 64-bit FIFO

UART 0 and 1 Support nrts0, ncts0, nrts1, and ncts1

Supports high-speed operations.

Handshakes are supported.

The following describes the transmission and receipt of data, interrupt generation, baud rate generation, loop mode, infrared mode, and automatic traffic control mode.

3. Data Transmission

The sent data frame can be programmed, including a start bit, 5 ~ 8-Bit Data bit, the parity bit and one or two stop bits. These can be controlled through the ulconn Linear Controller. The sender can generate termination conditions, which can force the serial port to output 0 status within the transmission time of a frame.

The data framefor transmission is programmable. it consists of a start bit, 5 to 8 data bits, an optional parity bit and 1 to 2 Stop bits, which can be specified by the linecontrol register (ulconn ). the transmitter can also produce the breakcondition, which forces the serial output to logic 0 state for one frametransmission time. this block transmits break signals after the presenttransmission word is transmitted completely. after the break signal transmission, it continuously transmits data into the Tx FIFO (TX holding register in thecase of non-FIFO mode ).

4. Data Reception

The received data frame can be programmed, including a starting bit, 5 ~ 8-Bit Data bit, the parity bit and one or two stop bits. These can be controlled through the ulconn Linear Controller. The receiver can detect overflow errors, parity errors, frame errors, and termination conditions. You can set an error flag for each error.

Overrun error refers to overwriting a new data before it is read.

Parity error indicates that the receiver detects an unexpected parity condition.

Frame Error indicates that the received data is not stopped.

Break condition indicates that rxdn is always in the 0 state when it exceeds a data frame.

When the receiver does not receive any data within the three-character period (its interval is based on the Character length) and the rxfifo is null, a timeout condition is generated.

 

5. Auto Flow Control (AFC)

The uart0 and uart1 in support Automatic Control of nrts and NCTS signals. In this way, it can connect to an external UART. If you want to connect UART to modem.

You must disable automatic flow by setting umconn and control nrts through software. UART writes data to the FIFO only when the NCTS signal is valid. In automatic traffic control, NCTS indicates that the other UART is ready to receive data. Before receiving data, if the FIFO has more than two free bytes, The nrts is set to valid. When the free byte space is less than 1, set nrts to invalid.

There are many registers in the serial port, but you can configure them as needed.

The compiled serial port program is as follows:

void Uart_Init(void){    // UART I/O port initialize (RXD0 : GPA0, TXD0: GPA1)    rGPACON = (rGPACON & ~(0xff<<0)) | (0x22<<0);    // GPA0->RXD0, GPA1->TXD0    rGPAPUD = (rGPAPUD & ~(0xf<<0)) | (0x1<<0);        // RXD0: Pull-down, TXD0: pull up/down disable    // Initialize UART Ch0    rULCON0 = (0<<6)|(0<<3)|(0<<2)|(3<<0);                    // Normal Mode, No Parity, 1 Stop Bit, 8 Bit Data    rUCON0 = (0<<10)|(1<<9)|(1<<8)|(0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0);    // PCLK divide, Polling Mode    rUFCON0 = (0<<6)|(0<<4)|(0<<2)|(0<<1)|(0<<0);            // Disable FIFO    rUMCON0 = (0<<5)|(0<<4)|(0<<0);                        // Disable Auto Flow Control    rUBRDIV0 = 35;                                    // Baud rate    rUDIVSLOT0 = 0x80;//aSlotTable[DivSlot];}void Uart_SendByte(int data){    while(!(rUTRSTAT0 & 0x2));   //Wait until THR is empty.    //_Delay();    WrUTXH0(data);}void Uart_SendString(char *pt){    while(*pt)        Uart_SendByte(*pt++);}//=====================================================================char Uart_GetCh(void){              while(!(rUTRSTAT0 & 0x1)); //Receive data ready        return RdURXH0();   }char Uart_GetKey(void){        if(rUTRSTAT0 & 0x1)    //Receive data ready            return RdURXH0();        return 0;    }