Deep understanding of Linux memory management

Deep understanding of Linux memory management
1. Memory Address

Taking Intel's central processor as an example, in a 32-bit Linux system, the basic unit of physical memory is Byte, and one Byte has eight binary digits. Each memory address points to one byte. After the memory address is 1, the address of the next byte is obtained. The address used to indicate the actual location of the physical memory.Physical address(Physical Address ). The Process Code, process data, and stack data that the CPU is executing are temporarily stored in the physical memory.

Linear address(Linear Address, or Virtual Address) is based on the following considerations:

(1) isolate the memory address space used by different processes;
(2) improve memory usage;
(3) determine the address when the program is running;

(4) extended memory, that is, run the program with an internal layer greater than the physical memory

The middle layer between the physical address and the program. The virtual address range corresponds to the addressing capability of the CPU, and the virtual address range of 32-bit CPU is 0x00000000 ~ 0 xFFFFFFFF, that is, the maximum virtual memory is 2 ^ 32 Bytes = 4 GB; the maximum virtual memory of the corresponding 64-bit CPU is 2 ^ 64 Bytes, however, at present, most operating systems and applications do not need such a large virtual address space, and a 64-bit long address will increase system complexity and address conversion costs, therefore, the current x86-64 architecture only uses the virtual address low 48 bits (0 ~ 47) Fill in 48-bit values as virtual addresses ~ Therefore, the maximum virtual memory of a 64-bit CPU is 2 ^ 48 = 256 TB. Generally, the physical address space is only a subset of the virtual address space.

To improve memory management efficiency and make full use of the virtual space, you can set the maximum bit (PG, paging flag) of the CPU's CR0 register, and enable the paging mechanism to divide the virtual space into several pages, manage and use virtual space by page frame. The page size specified by the physical memory is 4096 Bytes, 8192 Bytes, 2 MB, 4 MB, etc., because the content stored in the virtual space page is actually stored in the physical memory, therefore, the size of the virtual space is also paginated. The size of common pages is 4 kb.

In modern computer systems, programmers do not need to directly operate on physical addresses. Instead, the operating system allocates virtual addresses for execution by page frame. Each page frame can be mapped to any available physical memory page. When the CPU executes a program process, the CPU sends a read or write operation on the corresponding virtual address. hardware devices (MMU, memory management unit, are generally integrated into the CPU chip) after analyzing the virtual address, query the page table and calculate it, map the virtual address to a physical address, and then use the beiqiao chip (the main function of beiqiao chip is to communicate between CPU and physical memory) connect to the memory bus so that the CPU can access the Process Code and data in the physical memory.

Logical Address(Linear Address) refers to the internal Address offset of the program. This address is based on the program entry address allocated by the operating system, and specifies the address of the operands or commands in the program. The logical address is the address directly manipulated by the programmer. For example, in C Programming, defining an int variable, and then using the get address operator (& var) to get the address is the logical address.

The logical address consists of the Segment Selector and the Offset. The Segment Selector is a 16-bit (2 bytes) unsigned number, the segment offset is a 32-bit unsigned number. As shown in.

Figure 1 Segment Selector Fields <喎?http: www.bkjia.com kf ware vc " target="_blank" class="keylink"> Keys + keys/rysew0bPM0PLE2sjdu/K5/keys + 3bbOtcijrLLZ1/keys + 7XExNrI3cjnzbwyy/keys "http://www.2cto.com/uploadfile/Collfiles/20141113/2014111309173162.png" alt = "\">

Figure 2 Segment Descriptor

Base Address: 32 bits in total. It points to the linear Address of the first byte of the current segment. The Limit part has a total of 20 bits, which indicates the offset of the last byte of the virtual space in this segment relative to the first byte, so it can also represent the length of the segment. Different from the page (with a fixed length of 4 kb), the segment length varies according to the program content. In addition, if the flag is set to 0, the offset increases by 1 and the address value increases by 1 byte, the maximum length of this period is 1 byte * 2 ^ 20 = 1 MB; if the flag is set to 1, the offset is increased by 1 and the address value is increased by 4 KB. The maximum length of this period is 4 KB * 2 ^ 20 = 4 GB.

During the process execution, when a command needs to access the memory, first obtain the corresponding linear address based on the logical address, and then obtain the physical address based on the linear address. The process of obtaining a linear address based on the Logical Address is shown in step 3.

Figure 3 Translating a Logical Address

The CPU provides the CS register to temporarily Save the segment Selection Characters of the Process Code segment being executed, the DS register temporarily saves the segment Selection Characters of the process data segment, and the SS register temporarily saves the segment Selection Characters of the stack differentiation segments. In this way, when converting the logical address, the CPU determines whether the segment descriptor is in GDT or LDT Based on the segment selector currently stored in CS (see figure 1, the Index part determines the location of the segment descriptor in the table (GDT or LDT), so that the segment descriptor corresponding to the logical Address can be found. The starting linear Address of the segment is found based on the Base Address in the segment descriptor, you can use the starting address and the offset in the instruction logical address to obtain the actual linear address pointed to by the instruction.

Due to the association of the segmentation mechanism and Intel processor, the segment-based memory management may not be supported on other hardware systems. Therefore, in Linux, the operating system tends to manage the memory by page. In User Mode, all processes share User code segments and User data segments. In user mode, all processes use the Base Address part of the segment descriptor of the code segment to point to the linear Address 0x00000000, and the Base Address part of the segment descriptor of the Data Segment also points to the linear Address 0x00000000; in Kernel Mode, all processes share the Kernel code segment and Kernel data segment. The Base Address section of the segment descriptor used by all kernel processes points to the linear Address 0x00000000, and the Base Address section of the segment descriptor of the Data Segment also points to the linear Address 0x00000000. The G bit of the above segment descriptor is set to 1, and the virtual space corresponding to the segment ranges from 0 to 2 ^ 32, corresponding to the maximum virtual space of the entire 32-bit CPU.

The above solution solves the problem where other hardware platforms do not support segment management and greatly simplifies the address translation operation. However, in theory, the linear space available for each process is 4 GB, that is, the process shared field table, the purpose of isolating the process memory with segment boundaries cannot be achieved. Therefore, in Linux, an independent page table is allocated to each process, relying solely on the paging mechanism to provide memory protection and process isolation. Next, we will detail the paging mechanism.

3. Paging mechanism for memory management

The paging Mechanism regards the entire linear address space and the entire physical memory as composed of many storage blocks of the same size and uses these blocks as pages (each unit is called a page after the virtual space is PAGED) or page frames (each unit is called a page frame after the physical memory paging) for management. When memory access is not considered, any page of the linear address space can be mapped to any page frame in the physical address space theoretically. The most common paging method is to split pages in units of 4 kb, and ensure that the page address boundary is aligned, that is, the starting address of each page should be divisible by 4 kb. Under the unit of 4 kb, the virtual space of 32-bit machines is divided into 2 ^ 20 pages. Because the virtual address is mapped to all page frames of the same size and the page boundary is aligned, the last 12 digits of the virtual address can be directly used as the low 12 digits of the physical address.

To save the memory space required for storing the page table (2 ^ 20 * 4B = 4 M), the 32-bit operating system usually uses two-level page table structure to record the Page Status of the virtual address space. Therefore, each virtual address is composed of three parts. The top 10 digits are the index of the content in the Page Directory. The top 10 digits are the index of the Page table, the low 12 bits are used as the offset of the corresponding physical address in the page frame.

Figure 4 Paging mechanic

The page Directory is saved in the CR 3 register and can be accessed directly. During access, the index is indexed with a linear address height of 10 bits. The 32-bit page Directory items of the corresponding index are retrieved directly. The structure of the 32-bit Page Directory item 4 is shown in the Page Directory section. The 20-bit height of the Directory item is used to indicate the 20-bit height of the physical address of the Page table corresponding to the Directory item in the memory, the entry address of the 1024 page table can be provided for the 1024 directory items. The low 12 bits of a directory item are some flags. The P flag indicates whether the page table corresponding to the current directory item is in memory. The U flag indicates the page access permission corresponding to the current directory item; the S flag indicates that the page size is 4 kb or 4 MB. In addition, because each page Directory item has a length of 32 characters, that is, 4 bytes, there are a total of 1024 page Directory items in the page Directory, so the total size of the page Directory is 4 kb.

The page table is stored in the memory. The length of the page table item is 32 bits, and each page table contains 1024 page table items. The size of each page table is 4 KB. When a page table is stored in the memory, it is aligned with the size of the physical page (4 kb). Therefore, the last 12 digits of the physical memory address of each page table are 0. The 20-bit high of the physical address is specified by the 20-bit high in the page Directory corresponding to the page table, so that the page table in the physical memory can be found. After the page table is found, the 32-bit page table items corresponding to the index are retrieved using the 10-bit middle of the linear address as the index. Similar to the page Directory item, the page table item height is 20 bits to give the starting physical address of the corresponding page frame. The low 12 bits of the page table items are about the page flag.

The page frame corresponds to the physical memory. After finding the 20-bit high starting physical address of the page frame based on the previous two steps, because the physical memory is divided into page frames by 4 kb, therefore, the low 12-bit physical address of the starting page frame is 0. In this way, the starting physical address of the page frame is obtained by adding 20 bits and 12 bits. After the page frame is found, the low 10 digits of the linear address are used as the offset, and the physical address corresponding to the linear address can be found after the starting physical address of the previous page frame is added. It should be noted that the ing between the page frame and the page table item is not fixed. The page table item points to the top of the page first, the virtual page, the content of the virtual page is then stored in any suitable page frame.

The operating system allocates virtual address ranges for each process by page. Theoretically, a maximum of 4 GB of virtual memory can be used according to program requirements. However, because the operating system needs to protect the kernel process memory, the virtual memory of the kernel process is separated from the virtual memory of the user process. The former has 1 GB of virtual memory and the latter has 3 GB of virtual memory. When a process is executed, the page Directory of the page allocated by the operating system will be loaded to the Cr 3 register, and the page table will be loaded to the physical memory. When a paging unit converts a linear address to a physical address, it checks whether the current process has the permission to access the page and whether the page data corresponding to the linear address is in the physical memory, if the preceding conditions are not met, the paging unit generates a page error and terminates the process or loads the corresponding paging data to the physical memory.

4. physical address extension

Physical Address Extension is a unique virtual Address paging Method on Intel 32-bit CPU. Theoretically, a 32-bit CPU has 32 memory addressing lines that can access up to 4 GB of physical memory. in Linux, user-mode programs require linear address space, therefore, the maximum amount of physical memory that the kernel can access is 1 GB. However, with the development of computer software, a 32-bit computer may run many processes simultaneously, and these processes need more than 4 GB of memory, therefore, Intel has added 4 memory addressing lines for its 32-bit CPU, totaling 36, so that the physical memory supported by the CPU is increased to 2 ^ 36, that is, 64 GB. When the physical memory is extended, the virtual address range is 4 GB. So that 32-bit applications continue to use the 32-bit address, the maximum virtual memory available for each process is still 4 GB.

64 GB of physical memory is divided into 2 ^ 24 page frames under a 4 kb page, and the last 12 digits of the starting physical address of each page frame are still 0, however, the first 24 digits must be provided by the page table. As we know, in the regular paging, the page table item is 32 bits, and only 20 bits can be provided as the 20-bit physical address that points to the page frame, which cannot meet the addressing needs of the 36-bit system. This problem can be solved by adding the total length of the page table item. To ensure the boundary alignment of 4 kb, we increase the length of the page table item to 64 bits, the size of the page table is 4 kb. Therefore, a page table contains only 512 page table items (2 ^ 12/8 ).

Correspondingly, the page Directory must adapt to the 36-bit physical memory addressing capability. The length of each page Directory item also changes to 64-bit, and the page Directory size remains 4 kb, there are only 512 page Directory items in a page Directory. Such a page Directory can retrieve a total of 512*512 = 2 ^ 18 pages, and the virtual address space has a total of 2 ^ 20 pages, so a total of 4 Page directories are required.

A new layer is added to the Page Directory between the Controller and the Page Directory. The new layer is the Page Directory Pointer Table ). The page Directory pointer table contains four 64-bit pointers pointing to the preceding four page directories. The page Directory Index Table is loaded to the first 4 GB of 64 GB memory (physical address 0x00000000 ~ 0 xFFFFFFFF), and the starting physical address of the index table in the directory on this page is saved in.

After the physical extended addressing mode is enabled, the method for converting a linear address to a physical address is quite different from that before. The specific process is shown in step 5.

Figure 5 Linear Address Translation with PAE

First obtain the physical address of the page pointing table from the IP address of the object, and then use the linear address of 30 ~ The 31-bit index is used to obtain the page Directory. Next 21 ~ 39 bits (a total of 9 bits, providing indexes for all 512 page Directory items) can help locate the page table corresponding to the linear address, 12 ~ 20 (9 bits in total, providing the physical addresses of all 512 page table items) helps you find the physical address of the page frame corresponding to the linear address.

5. 64-bit operating system paging Mechanism

The addressing capability of 64-bit machines is 2 ^ 64 Bytes, but so much virtual memory is not used in reality, the 64-bit addressing method can also lead to adverse factors such as increasing addressing time and wasting memory space. Therefore, in practical applications, uses a 48-bit addressing mode for 64-bit hosts (up to TB physical memory is supported ). Similarly, if the physical memory is divided into 4 kb page frames, a 48-12 = 36-bit physical address is required to determine the page frame position. To reduce the physical memory required to store the page table and enable memory access, You can distribute the page table by adding two page Directory layers. In Linux, layer-4 paging is used for this purpose.

The system will create a process to execute the program, then load the program or program fragment, and then start to execute the code segment in sequence. In this process, the operating system generally does three things:

(1) create an independent virtual address space (range) for the Process)

For example, in a 32-bit system with regular paging status, if the operating system finds that the total number of commands and data of the program to be executed is 32 KB, the operating system allocates 8 pages of virtual memory space for the process, the page Directory and page table are allocated, the page Directory is loaded into S3. the page table used by the process is loaded into the memory. However, it does not load commands and data into the memory.

(2) read the executable file header of the program, and establish a ing between the virtual space and the logical address of the code segment and data segment in the executable file.

In this step, program commands and data are mapped to the virtual memory space.

(3) set the CPU instruction register to the entry address of the executable file to start running.

When executing a program, if the current command or data is in the virtual address space and is not actually in the physical memory (the commands or data are not loaded to the physical memory in the first two steps ), A page error occurs. Then, the operating system allocates an idle physical page frame from the physical memory, and copies the data of the virtual address page from the disk to the physical page frame, create a ing relationship between page table items and page frames. As the process is executed, page errors are generated constantly, and the operating system will respond to errors on each page and allocate physical memory page frames to the process. However, the physical memory is limited, and the physical memory that can be allocated to a process is also limited. After all available physical memory is allocated to the process, if the process continues to throw a page error to request more physical memory, the operating system will replace the operating algorithm based on its own page, to ensure the normal operation of the process, the previous physical memory page frames allocated to the process are withdrawn and distributed to the process again.