Describes in detail the driving circuit of the MOs.

Source: Power Supply Network

Keywords: MOS Structure switch Drive Circuit

When using MOS to design a switching power supply or motor drive circuit, most people will consider the mos on-resistance, maximum voltage, maximum current, and so on. Many people only consider these factors. Such a circuit may work, but it is not excellent. It is not allowed as a formal product design.

The following is my summary of the basis of the mos and MOS driving circuit. I have referred to some materials, not all original. This includes the introduction, features, drivers, and application circuits of MOS tubes.

1. Type and structure of MOS

One type of FET (the other is JFET), which can be manufactured as an enhanced or depletion type. There are four types of p-channel or N-channel, however, in practice, only enhanced NMOS and enhanced p-mos are used. Therefore, NMOS or PMOS are usually used.

We do not recommend that you use the depletion MOS. For the two Enhanced MOs, NMOS are commonly used. The reason is that the conduction resistance is small and easy to manufacture. Therefore, NMOS are generally used for switching power supplies and motor drives. In the following introduction, NMOS is also used.

Parasitic Capacitance exists between the three pins of the mos tube. This is not what we need, but is produced by manufacturing process restrictions. The existence of parasitic capacitors makes it difficult to design or select the driving circuit, but there is no way to avoid it. I will introduce it in detail later. A parasitic diode exists between the drain pole and the source pole. This is called a body diode, which is very important in driving inductive loads (such as motors. By the way, the diode only exists in a single MOS tube and is usually unavailable in an integrated circuit chip.

2. On-going characteristics of MOS Tubes

As a switch, the switch is closed.

For NMOS, if the value of vgs is greater than a certain value, it will be turned on. It is suitable for the case when the source pole is grounded (low-end drive), as long as the gate voltage reaches 4 V or 10 v.

When the PMOS feature is smaller than a certain value, the vgs will be turned on. It is suitable for use when the source pole is connected to VCC (high-end driver ). However, although PMOS can be easily used as a high-end driver, NMOS is usually used in high-end drivers due to the large conduction resistance, expensive price, and few replacement types.

3. MOS switch loss

Whether it is NMOS or PMOS, there is a turn-on resistance after the turn-on, so that the current will consume energy on this resistance, the energy consumed is called the turn-on loss. Selecting a MOS tube with a small conduction resistance reduces the conduction loss. At present, the on-resistance of low-power MOS tubes is usually around dozens of S, and several s are also available.

Mos must not be completed in an instant at the end of the tunnel and tunnel. The voltage at both ends of MOS has a descent process, and the flowing current has a rising process. During this period, the loss of the mos tube is the product of the voltage and the current, which is called the switch loss. Generally, the switch loss is much greater than the conduction loss, and the faster the switch frequency, the larger the loss.

The product of transient voltage and current is very large, resulting in great losses. The switching time can be shortened to reduce the loss during each conduction; the switching frequency can be reduced to reduce the number of switches per unit of time. Both methods can reduce the switch loss.

4. MOS drive

Compared with bipolar transistor, it is generally considered that the mos do not require current for conduction, as long as the GS voltage is higher than a certain value. This is easy to do, but we still need speed.

In the structure of the mos tube, it can be seen that there is a parasitic capacitor between GS and Gd, while the driving of the mos tube is actually charging and discharging the capacitor. Charging a capacitor requires a current, because the capacitor can be regarded as a short circuit in an instant, so the instantaneous current will be relatively large. When selecting/designing the mos drive, the first thing to note is the size of transient short-circuit current.

Second, it is generally used for NMOS of high-end drivers. The gate voltage must be greater than the source pole voltage during conduction. The source voltage is the same as the drain voltage (VCC) when the high-end drive MOS tube is turned on, so the gate voltage is larger than VCC by 4 V or 10 v. If you want to obtain a voltage greater than that of VCC in the same system, you need a dedicated Boost Circuit. Many motor drivers are integrated with a charge pump. It should be noted that the appropriate external capacitor should be selected to get enough short-circuit current to drive the mos tube.

The 4 V or 10 V above is the on-voltage of the commonly used MOS tube. Of course, there must be a certain margin during the design. The higher the voltage, the faster the conduction speed, and the smaller the conduction resistance. At present, MOS with lower conduction voltage are also used in different fields, but in 12 V automotive electronic systems, it is enough to conduct 4 V.

For more information about the driving circuit and loss of MOS, see the Microchip Corporation's an799 matching MOs drivers to ipvets. The description is very detailed, so I don't plan to write more.

5. MOS Application Circuit

The most notable characteristic of MOS is that they have good switching characteristics, so they are widely used in circuits requiring electronic switches. Common ones include switching power supplies and motor drives, and lighting dimming.

The current MOS driver has several special requirements,

1. Low-voltage applications

When the 5 V power supply is used, if the traditional tumble-column structure is used at this time, the must voltage drop of the transistor is about 4.3 V, resulting in the actual voltage added to the gate is only v. At this time, there is a certain risk for us to choose a MOS tube with a nominal gate voltage of v.

The same problem occurs when 3 V or other low-voltage power supply is used.

2. Wide Voltage Application

The input voltage is not a fixed value and changes with time or other factors. This change causes the drive voltage provided by the PWM circuit to the mos tube to be unstable.

To ensure the safety of MOS tubes at high gate voltage, many MOS tubes have built-in voltage control tubes that forcibly limit the gate voltage amplitude. In this case, when the supplied driving voltage exceeds the voltage of the voltage regulator, it will cause a large static power consumption.

At the same time, if the gate voltage is reduced by using the principle of resistance partial pressure, the mos Tube works well when the input voltage is relatively high, and the gate voltage is insufficient when the input voltage is reduced, resulting in incomplete conduction, thus increasing power consumption.

3. Dual-voltage applications

In some control circuits, the logical part uses a typical 5 V or 3 V digital voltage, while the power part uses a 12 V or higher voltage. The two voltages are connected in a common location.

This puts forward a requirement that a circuit should be used to allow the low voltage side to effectively control the mos at the high voltage side. At the same time, the mos at the high voltage side will also face the problems mentioned in 1 and 2.

In these three cases, the figure tengzhu structure cannot meet the output requirements, and many ready-made MoS drive ICS do not seem to contain the gate voltage limit structure.

So I designed a relatively general circuit to meet these three requirements.

The circuit diagram is as follows:

Figure 1 driving circuit For NMOS 2 driving circuit for PMOS

Here I will only make a simple analysis on the NMOS drive circuit:

The two voltages can be the same, but the VL value should not exceed.

Q1 and Q2 form an inverted totem bar to achieve isolation, while ensuring that the two drive tubes Q3 and Q4 do not turn on at the same time.

R2 and R3 provide the PWM Voltage Reference. By changing this reference, the circuit can work in a steep position of the PWM signal waveform.

Q3 and Q4 are used to provide the driving current. Because of the conduction, Q3 and Q4 have only one VCE Pressure Drop relative to the two Gnd, which is usually about 0.3v, VCE is much lower than 0.7v.

R5 and R6 are feedback resistors used for gate voltage sampling. The sampled voltage generates a strong negative feedback on the base poles of Q1 and Q2 through Q5, thus, the gate voltage is limited to a finite number. This value can be adjusted by R5 and R6.

Finally, R1 provides the base current limit for Q3 and Q4. R4 provides the gate current limit for MOS, that is, the ice limit for Q3 and Q4. When necessary, you can parallel the acceleration capacitor on the R4.

This circuit provides the following features:

1. Use low-end voltage and PWM to drive high-end MOS tubes.

2. Use a small PWM signal to drive the mos tubes with high gate voltage requirements.

3. Peak gate voltage limit

4. Input and Output Current limits

5. Low Power Consumption can be achieved by using proper resistance.

6. PWM signal inversion. NMOS does not need this feature. It can be solved by a front inverter.

When designing portable devices and wireless products, improving product performance and extending battery time are two problems that designers need to deal. DC-DC converter has the advantages of high efficiency, large output current, small static current and so on, it is very suitable for power supply for portable equipment. At present, the main development trend of DC-DC Converter Design Technology are as follows: (1) High Frequency Technology: with the increase of switching frequency, the volume of switching converter also decreases, power density has been greatly improved, dynamic response is improved. The switch frequency of the small power DC-DC converter will rise to megahertz. (2) Low Output Voltage Technology: With the continuous development of semiconductor manufacturing technology, the operating voltage of microprocessor and portable electronic devices is getting lower and lower, this requires that future DC-DC converters can provide low output voltage to meet the requirements of microprocessor and portable electronic devices.

The development of these technologies puts forward higher requirements for the design of the power chip circuit. First of all, as the switching frequency continues to increase, it puts forward high requirements on the Performance of switching components, at the same time, it is necessary to have the corresponding switch element driving circuit to ensure that the switch element works normally at a switch frequency up to megahertz. Secondly, for battery-powered portable electronic devices, the operating voltage of the circuit is low (taking lithium battery as an example, the operating voltage is 2.5 ~ 3.6 V). Therefore, the operating voltage of the power supply chip is low.

Mos tube has very low on-resistance, low energy consumption, in the current popular high-efficiency DC-DC chip using MOS tube as power switch. However, due to the high parasitic electrical capacity of the mos tube, the gate capacitance of the NMOS switch is usually as high as dozens of skins. This puts forward higher requirements for the design of the drive circuit of the switch tube of high-frequency DC-DC converter.

In the low-voltage ULSI design, multiple logic circuits of CMOS and BiCMOS adopt a self-lifting boost structure and are used as driving circuits for large-capacity loads. These circuits can work normally under 1 V voltage supply conditions, and can be 1 ~ The operating frequency of 2pf can reach dozens or even hundreds of megahertz. In this paper, the self-lifting boost circuit is used to design a kind of high load capacitive drive ability, suitable for low voltage, high switching frequency boost DC-DC converter driver circuit. The circuit is designed based on the Samsung ahp615 BiCMOS process and verified by the simulation of the heat transport system. When the power supply voltage is 1.5 V and the load capacitor is 60pf, the working frequency can reach more than 5 MHz.

Self-lifting Boost Circuit

The schematic 1 of the Self-lifting Boost Circuit is shown in. The so-called auto-lifting boost principle is to input a square wave signal in the input end, and use the cboot capacitor to raise the-point voltage to the VDD level, in this way, a square wave signal with a high level higher than that of VDD can be output at the B end. The working principle is as follows.

When vin is high, NMOS N1 is turned on, PMOS P1 ends, and the C-point potential is low. At the same time, N2 is turned on. P2 is turned on when the gate potential of P2 is low. In this case, the Point potential is about VDD, and the voltage at both ends of the cboot capacitor is UC ≈ VDD. Due to N3 conduction and P4 cutoff, the potential of point B is low. This period is called the pre-charging cycle.

When Vin becomes low, NMOS tube N1 ends, PMOS tube P1 is turned on, and the C-point potential is high, which is about VDD. At the same time, N2 and N3 ends and P3 is turned on. This increases the gate potential of P2 and ends at P2. At this time, the-Point potential equals to the C-point potential plus the voltage at both ends of the cboot capacitor, which is about 2vdd. And P4 conduction, so B points Output High Level, and higher than VDD. This period is called a self-lifting boost cycle.

In fact, the B-point potential is related to the size of the load capacitor and the cboot capacity, which can be adjusted according to the design requirements. The specific relationship will be discussed in detail during the introduction of circuit design. In Figure 2, the relationship between the in potential at the input end and the two potentials A and B is given.

Driving Circuit Structure

The circuit diagram of the driving circuit is shown in figure 3. The driving circuit adopts the totem output structure design, and the uplink driving tube is NMOS tube N4, transistor Q1 and PMOS tube P5. The drop-down driver is NMOS n5. In the figure, Cl is the load capacitor, and CPAR is the parasitic capacitor of point B. The circuit in the dotted box is the self-lifting Boost Circuit.

The design idea of the driving circuit is to use the self-lifting boost structure to raise the gate (point B) of the upstream driving tube N4, so that the UB> VDD + Vth, the NMOS tube N4 operates in an online zone, greatly reducing vdsn4, and finally achieving a high output level of VDD. When the output power is low, the drop-down drive tube itself is working in the online zone to ensure the output of low-level Gnd. Therefore, the design requirements can be met without the need to add a self-lifting circuit.

Considering that this driving circuit is applied to the switch drive of boost DC-DC converter, the load capacitor Cl is very large, generally can reach dozens of skin method, but also need to further increase the output current capacity, therefore, the transistor Q1 is added as the uplink drive tube. In this way, the input end changes from high level to low level, Q1 conduction, by N4, Q1 at the same time to provide current, the out-end potential rises rapidly, when the out-end potential rises to the VDD-VBE, Q1 cutoff, n4 continues to provide current to charge the load capacitor until the out-end voltage reaches VDD.

When the out end is high, the Point potential will decrease due to the charge leakage on the cboot capacitor. This reduces the B-point potential and the n4. At the same time, due to the same reason, the out-end potential also drops, so that the output high level cannot be kept in VDD. To prevent this phenomenon, the PMOS P5 is added as the pull-up driving tube to supplement the leakage charge of CL at the out end and maintain the high level of the out end during the entire conduction period. The transmission characteristics of the driving circuit are shown in figure 4. (A) Is the transient response of the rising edge, and (B) is the transient response of the falling edge. As shown in figure 4, the rising edge of the drive circuit is obviously divided into three parts, which are the dominant periods for the three Driver tubes. The first stage is Q1 and N4, and the output voltage is quickly increased. The second stage is N4, so that the output level reaches VDD. The third stage is P5, maintain that the output height is VDD. In addition, the increase time can be shortened and the decrease time can meet the requirements of working frequency above the megahertz level.

Precautions and simulation results

Capacity cboot Size Determination

The minimum value of cboot can be determined according to the following methods. During the pre-charging period, the charge on the capacitor cboot is vddcboot. The charge on the parasitic capacitance (counted as Ca) at point A is vddca. Therefore, during the pre-charging period, the total charge at point A is

Q _ {A1} = V _ {dd} C _ {boot} + V _ {dd} C _ {A} (1)

The point B potential is Gnd, so the charge on the point B parasitic capacitor CPAR is 0.

In the self-lifting boost period, in order to bring the out-end voltage to VDD, the minimum B-point potential is VB = VDD + vthn. Therefore, the charge on the parasitic capacitor CPAR at point B is

Q _ {B} = (V _ {dd} + V _ {Thn}) CPAR (2)

Ignore the pressure drop at both ends of the mos P4 source leakage. The charge on the cboot is vthncboot, and the charge of the-Point parasitic capacitor CA is (VDD + vthn) Ca. The total charge of Point A is

Qa2 = V _ {Thn} C _ {boot} + (V _ {dd} + V _ {Thn}) C _ {A} (3)

At the same time, there are

Q _ {B} = Q _ {A}-Q _ {A2} (4)

Comprehensive (1 )~ (4) Available

C _ {boot }=\ frac {v _ {dd} + V _ {Thn }}{ V _ {dd}-V _ {Thn} CPAR + \ frac {v _ {Thn }}{ V _ {dd}-V _ {Thn} C _ {A }=\ frac {v _ {B }}{ V _ {dd }- V _ {Thn} CPAR + \ frac {v _ {Thn} {v _ {dd}-V _ {Thn} C _ {A} (5)

From formula (5), we can see that cboot increases with the input voltage decreasing and VB increases with the B-point voltage. The B-point voltage directly affects the on-resistance of N4, which also affects the rising time of the drive circuit. Therefore, in actual design, the cboot value must be greater than the formula (5), which can increase the B-point voltage, reduce the N4 on-resistance, and reduce the rising time of the drive circuit.

P2 and P4 dimensions

After reorganizing formula (5:

V _ {B} = ({v _ {dd}-V _ {Thn }) \ frac {C _ {boot }}{ CPAR}-V _ {Thn} \ frac {C _ {A }}{ CPAR} (6)

From formula (6), we can see that the parasitic capacitance of point A and point B reduces the potential of point B During the auto-boost period. In actual design, in order to obtain the appropriate B-point potential, in addition to increasing the cboot size, the parasitic capacitance of A and B should be minimized. During design, the size of pre-charged PMOS tube P2 should be as small as possible to reduce the parasitic capacitance ca. For the parasitic capacitor CPAR at point B, it is mainly the gate parasitic capacitor of the upstream drive tube N4, and the source leakage parasitic capacitor of the mos P4 and N3 is only a small part. In the previous analysis, we ignored the source leakage voltage of P4, so we should increase the width-to-length ratio of P4 as much as possible during design, so that the source leakage voltage in the Self-lifting boost cycle is very small, can be ignored. However, the size of P4 cannot be too large. It is necessary to ensure that the source parasitic capacitance of P4 is far smaller than the gate parasitic capacitance of the upstream driving tube N4.

Trap potential problems

As shown in 3, the N-Well of PMOS P2, P3, and P4 are connected to the self-lifting boost node. In this way, the source/leakage-trap conduction is prevented during the self-lifting boost period. This can also prevent the occurrence of latches caused by parasitic SRC when the source/drain-trap is positive.

The trap bias potential of the upstream driving tube N4 should be connected to its source pole. It is best not to directly ground it. The purpose is to eliminate the influence of substrate bias on N4.

Simulation and verification results

The driving circuit is designed based on the Samsung ahp615 BiCMOS process and has been verified by the simulation of the high-performance hardware. In table 1, the simulation results of the rising time Tr and falling time tF of the circuit under different operating voltage and different load conditions are given. In Figure 5, the output waveform of the circuit operating at an input voltage of 1.5 V, a working frequency of 5 MHz, and a load capacitor of 60pf is provided.

As shown in table 1 and figure 5, the drive circuit works properly when the operating voltage is 1.5 V, the operating frequency is 5 MHz, and the load capacitor is up to 60 PF. It can be applied to low voltage, high frequency DC-DC converter as the driving circuit of the switch.

Conclusion

In this paper, a driving circuit with a BiCMOS totem structure is designed by using a self-lifting Boost Circuit. The circuit is designed based on the Samsung ahp615 BiCMOS process. It can work normally under V voltage supply conditions, and the working frequency can reach more than 5 MHz under the condition that the load capacitor is 60pf.

Describes in detail the driving circuit (switch) of the MOs)