Design and Implementation of Software Phase-Locked Loop Based on fixed point DSP

Design and Implementation of Software Phase-Locked Loop Based on fixed point DSP

[Date:]

Source: Electronic Technology Application Author: Jiang yikai Li guotong Yang genqing

[Font:Large Medium Small]

　

Low-track satellite communication is an important field in satellite communication applications in recent years. "Innovative No. 1" satellite is a small satellite developed by China with completely proprietary intellectual property rights for storage and forwarding communication, cascom handheld terminal is a low-power terrestrial handheld communication terminal specially developed for this small satellite. It supports a BPSK narrowband channel with a modulation data speed of kbps. Based on TI's 16-bit low-power Fixed-Point Digital Signal Processor TMS320VC5510 (with a maximum computing capability of 200 MIPS), the system uses software to implement a low-frequency digital receiver, this includes the Software Phase-Locked Loops (SPLL), which implements the carrier recovery function ). When a floating point algorithm is used to implement the Software Phase-Locked Loop, because the TMS320VC5510 is a fixed-point DSP processor and does not have a floating point processing unit, it can only use a compiler to generate a command to simulate floating point operations. The calculation requires 67.2 MIPS and the efficiency is very low, therefore, a fixed-point algorithm that can be executed on TMS320VC5510 is required to effectively reduce the computational workload. In this paper, a 48-Bit fixed-point extension precision algorithm is proposed to implement SPLL, which improves efficiency, reduces the amount of computation, and ensures the accuracy and dynamic range of loop computation.

1 Software Phase-lock loop

1.1 Structure of Software Phase-lock loop 

Figure 1 indicates the modem in the software digital receiver. It includes a carrier tracking loop consisting of an improved costas Loop [1.

 

 

After sampling, the intermediate frequency signal passes through digital mixing, filters out the high-frequency components, generates control signals through the improved costas loop, and controls the Numerical Control Oscillator (NCO) to obtain a new reference signal. The phase detector and loop filter structure 2 are shown in the figure.

 

 

1.2 Design of Software Phase-lock loop 

As shown in figure 2, SPLL is calculated by calculating the phase error, updating the intermediate variable of the loop, and outputting the control signal. Algorithm description can be expressed by pseudo code:

 

The interruption period in the algorithm description is the loop sampling interval.

After the interruption occurs, the first step is to read the same-phase data of the baseband and the same-phase data of the orthogonal data.

A is the baseband signal amplitude, and θ e is the phase error. The second step is to calculate the hardcoded homogeneous data multiplied by the phase error.

Formula (3), (5), and (6:

That is, the result of the hard decision of the same phase data is multiplied by the orthogonal item data and then multiplied by the normalization factor K_norm. The initial value of K_norm is determined by the initial values of I _baseband and Q_baseband,

Due to the regular Recovery Loop and AGC (Automatic Gain Control) loop, K_norm remains approximately constant during the demodulation process. Step 3 Update the loop intermediate variable s_pll (n ),

F0 is a fixed NCO center frequency. So far, a complete SPLL computing is complete.

In step 3 and Step 4 calculation, the ring filter coefficients C1 and C2 can pass the loop sampling interval T (or the loop update interval) determine the free loop frequency ω n and the damping coefficient of the loop, as shown in [2]:

KD is the gain of the phase detector. Because the same phase and orthogonal components of the baseband signal are normalized when the Software Phase-Locked Loop is implemented, Kd = 1; K0 is the gain of the numerical control oscillator, k0 = 2 π T. T is the reciprocal (1/76800) of the modulation data rate, and 0.707 is generally used for the ε. There is a frequency capture process before starting the carrier recovery. Through the 1024-point FFT, the maximum frequency difference between the received intermediate frequency signal and the Local Vibration Signal is not more than 75Hz. In addition, the system design requires that the capture time (pull in time) of spll be less than 50 ms, so that the free loop frequency ω N can be determined. ω n> 150 (rad · Hz), take ω n = 300 (rad · Hz ). K0, KD, ε, ω N, t are substituted into the formula (3), (4), C1 = 67.3273309, C2 = 0.1859953.

2-48-Bit fixed-point extension accuracy Algorithm

When the algorithm described in Figure 3 is directly implemented using the floating point operation in the C language on the tms320vc5510, only the C compiler can generate fixed-point commands to simulate floating-point operations. This method is very inefficient, and each loop computing consumes 875 instruction cycles. 67.2mips is required in a digital receiver with a modulation data rate of 76.8kbps. In order to reduce the computational workload of loop computation and keep floating point Computation with the advantage of large dynamic range and high accuracy, a 48-Bit fixed point extension precision computation method is proposed. Each operand involved in the operation is represented by three 16-Bit fixed points W2, W1, and W0 cascade. The 16-bit height is the integer part of the binary complement, the lower 32-bit is the decimal part of the binary complement code. The symbol bit is in the highest bit, also known as q15.32 format, as shown in 3.

 

 

The range of q15.32 values is (-32768,32768), and the decimal resolution is much more precise than the 16-Bit fixed-point representation. The following values are used to add (add_48), subtract (sub_48), and multiply (mult_48) three basic operations are used to describe the fixed-point extension accuracy algorithm. The operand X is composed of X2, X1, and x0. the operand y is composed of Y2, Y1, and Y0. The result W is composed of W2, W1, and W0. When the 48-bit addition operation is executed, w2w1w0 = x2x1x0 + y2y1y0, first add the fractional part x1x0 and y1y0, and save the result to w1w0. The generated carry is added to X2 and Y2, save the result to W2. When the 48-bit subtraction operation is executed, w2w1w0 = X2X1X0-Y2Y1Y0, first x1x0 minus y1y0, the result is saved to w1w0, generate a bits borrow, then the X2 minus Y2 and the bits borrow, save the result to W2. The product of the two q15.32 numbers is a q30.64 number. Due to the dynamic range and computing accuracy requirements for the previous implementation of spll, The q30.64 number can be two-way truncated to the 48-Bit fixed point of q15.32. The specific method is to retain the low 15 bits of the sign bit and integer, and the high 32 bits of the decimal part. The multiplication of 48-Bit fixed points is shown in Figure 4.

 

 

In addition to the above three basic operations: addition, subtraction, and multiplication, the 48-Bit fixed-point extension accuracy algorithm also includes the negative (neg_48) and data copy (move_48) operations. Negative operation: x1x0 is used to take the negative value, and the result is saved to w1w0. The bitwise borrow is generated, and 0 minus X2 and the bitwise borrow are used to save the result to W2. The data is copied, copy x1x0 to w1w0 and X2 to W2.

Based on the TMS320VC5510 programmable DSP, the 48-Bit fixed-point extension accuracy algorithm is used to implement SPLL. In the implementation process, a modular approach is adopted. First, encapsulate the entire SPLL loop computing into a callable C language function. Function parameters include C1, C2, K_norm, I and Q components of baseband signals, intermediate loop variables, and adjustment frequency. The Interrupt Routine (ISR) of DSP can directly call the loop computing function, and it is suitable for different carrier recovery loops by inputting different C1 and C2. In addition, the function is programmed in an assembly language to fully utilize the computing capability of the DSP, encapsulate the five basic operations of the 48-Bit fixed-point extended precision algorithm into macros written using assembly commands (macro). Call these macros against the computing process to complete the core computing part of SPLL. According to statistics, 132 instruction cycles are required for each loop calculation. The total calculation workload is 10.1 MIPS, Which is 67.2 of the Floating Point Algorithm calculation workload (14% MIPS.

The 48-bit extended precision algorithm is used to implement the SPLL in the software receiver, which solves the large amount of floating point algorithm operation. It also has the advantage of large dynamic range and high accuracy of floating point algorithms, it has been successfully applied to the ground handheld low-power communication terminal of "Innovative No. 1" satellite. In addition, the SPLL implementation algorithm proposed in this paper can be applied to other software receivers by modifying the loop filter coefficient, which has good scalability.