Design and simulation verification of integer multiplier based on Verilog HDL

Design and simulation verification of integer multiplier based on Verilog HDL

1. Pre-Knowledge

Integers are divided into short integers, medium integers, long integers, and only short integers are involved in this article. Short integer: Occupies a byte space,8 bits, where the highest position is the sign bit (the maximum bit is 1 is negative, the highest bit is 0 is a positive number), the value range is -127~127 .

Negative numbers are represented by positive negation plus 1. For example:

8 ' b0000_0100; represents the value:4, positive negation is:8' b1111_1011; plus 1 means:8' b1111_1100, the 4 is represented by:8' b1111_1100.

Similarly, negative values become positive by negative negation plus 1.

2. Design Ideas

How can I tell if a short integer is positive or negative?

Use the highest bit of a number,if (! A[7])//a is positive;if (b[7])//b is a negative value.

In the multiplication operation, the symbol of the result of the operation can be obtained by an XOR operation.

A Value	B Value	Results
Positive (0)	Positive (0)	Positive (0)
Positive (0)	Negative (1)	Negative (1)
Negative (1)	Positive (0)	Negative (1)
Negative (1)	Negative (1)	Positive (0)

3. Multiplier program Design ideas

First consider the input semaphore, there is a multiplier and the multiplier, there is a start instruction (start_sig), the equivalent of We enter the calculation formula in the calculator, and then press the next "= "number, get the final result.

Then consider the output signal, there is the result of the calculation, at the same time, after the calculation results, output an operation complete signal (done_sig).

Verilog HDL Program implementation of multiplication: with 8X5 for example, where 8 is the multiplier,5 is the multiplier, The meaning of the representation is 5 of 8 Add. Multiplication can be split into three steps to achieve :

Before the operation, obtain the multiplier and the sign bit of the multiplier, and then take the positive value of the multiplier and multiplier.

Isneg <= multiplicand[7]^multiplier[7];

Mcand <= multiplicand[7]? (~multiplicand+1 ' B1): Multiplicand;

Mer <= multiplier[7]? (~multiplier+1 ' B1): Multiplier;

4. Modelsim -based multiplier simulation verification

This article will describe in detail the Modelsim configuration process, convenient for later review.

(1) First set up the multiplier model, editing good Verilog HDL Program (learning Focus)

(2) associated Quartus and Modelsim-altera

Tools----Options----EDA tool options, select Simulation Tools, and add installation paths to the simulation tools. This article chooses the modelsim-altera.

(3) Set the simulation tool with the text format to be emulated,time scale.

Assignments----Settings----Simulation

Tool Name:

Format for output netlist:

Time scale:

Output directory: default setting

(4) automatically generate Test bench Template

Processing----start----start test Bench Template writer, the Test Benchis automatically generated when the operation is completed .

Open the Test Bench file, the entire project file will generate a simulation folder, open, found inside the "xxx.vt "file.

(5) Edit Test bench file

Follow the comments in the template file to populate the appropriate test program. (There are Brainiac)

In the test file, there is an initialization module, which is typically used to initialize the clock signal (CLK) and reset the entire circuit (rstn).

With the change of the parameter "#num", compared with the simulation waveform, it can be concluded that "#num" is the statement used to set the time.

First of all talk about how the multiplier works: first input multiplier and the multiplier, when the start_sig Signal High level, the multiplier began to work, according to the pre-written model one step after the completion of the operation,Done_sig Output high, representing the completion of the operation, the results of the operation output to the Product .

The 1.start_sig is changed from 0 to 1, and the multiplierbegins to operate (equivalent to the equal sign button on the calculator), and there is already a value for the multipliers and the input ports Done_sig in st0 status, the Representative has not completed the calculation.

2. The first step of the multiplication is calculated, and the output Product has the first step, but the done_sig signal remains st0 Status, representing the calculation is not yet closed

3. The second operation is completed and the result is output to the Product signal Line, but the done_sig signal remains st0 , the multiplier continues to work.

The 4.done_sig signal line changes from st0 to st1, and lasts a pulse period, at this point the multiplier completes the calculation,Product the data on the signal line is the final result of the multiplication operation.

The 5.done_sig state is back to st0, and now the start_sig signal is changed from 1 to 0 . , on behalf of the multiplier shutdown, stop working, always the multiplication algorithm inside the block statement will no longer execute.

 

(6) Add the edited Test bench file to the project

Assignments----Settings----Simulation

Select the Compile test bench option and click... "

New----

You need to populate the following:

Test Bench Name: is the name of the testbench file, whichis the file name of the ". VT" file.

Top level module in test bench: is the top module name of the Testbench file.

End simulation at: is the maximum time to simulate.

In the test bench files Panel, add the test bench file and click... "Find" . VT The path of the file, click Add , and then click OK .

Click OK.

Click Applyand click OK.

(7) Start simulation

Tools----Run EDA Simulation Tool----EDA RTL Simulation

Start the modelsim program automatically, that is, you can see the simulation waveform.

Design and simulation verification of integer multiplier based on Verilog HDL