Design Compiler Synthesis

Synthesis (synthesis) = conversion (translation) + Optimization (logic optimization) + mapping (gate mapping);

In the conversion phase, the circuitry described in HDL language is implemented with gate-level logic. For the circuit that DC uses the gate-level unit in the Gtech.db Library to implement the HDL language description, the initial non-optimized circuit is obtained. The integrated tool for optimization and mapping analyzes the initial circuit and removes redundant units. The path is optimized according to constraints (Environment constraints and design constraints), and the optimized circuit is mapped to the process library provided by the manufacturer.

The characteristics of the synthesis

1, the synthesis is the restriction condition-driven, the restriction condition is the comprehensive goal.

2, synthesis is based on the path, design compiler in the synthesis, will call the static Timing analysis tool Design timer to the circuit of the effective path of the static timing analysis, according to the time series analysis results of the circuit optimization.

DC Eight types of design entities in

Design: A circuit capable of accomplishing certain logic functions;

Unit (cell): an instance of a sub-design contained in a design;

Reference (Reference): The Reference object of the unit, i.e. the unit is the reference instance;

Port: The basic input output of the design;

Pin: Input output of the unit;

Wire Network (NET): interconnection between ports and pins;

Clock: The PIN or port that is the source of the clock signal;

Library: A collection of a set of units used in a synthesis.

DC you typically specify the following 4 Seed Library

Target Library: A process library that corresponds to a process library, a process provided by a foundry.

Link Library: It is used primarily to specify the target specified by the DC lookup, which is usually the destination Library.

Synthetic LIBRARY:DC The IP library that is used to convert the HDL code to the corresponding component when combined, for example, the symbol "+", which generates a class of adders by locating the IP library. By default, the DC uses its own IP library and, of course, the user can specify a different IP library if necessary.

Symbol Library: When using the graphical interface of the DC, i.e. DV, the symbols of various standard elements, such as the non-gate, are given on the schematic diagram.

GTECH Library

Synopsys's general process library, which comes from DC, is independent of the factory process. The components contained in the library represent only a certain logical function without any process parameters. The DC converts the HDL description into a circuit consisting of the GTECH Library Unit at translate

Reference documents:

[1] Initial DC experience. Http://www.eetop.cn/blog/html/23/422523-28716.html

[2] logical synthesis overview. Http://www.cnblogs.com/tianfei1201/archive/2012/10/12/2721555.html

[3] Design complier basic knowledge. Http://www.cnblogs.com/zeushuang/archive/2012/08/09/2629902.html

[4] Logic synthesis tool DC and Operation flow (1). Http://www.eetop.cn/blog/html/23/422523-28738.html

Design Compiler Synthesis