Design Concept of SDH optical interface of a programmable Switch

SDH optical interfaces are very important in programmable switches. Here we mainly introduce the design concept of SDH optical interfaces of programmable switches. With the rapid development of modern telecom networks, the synchronous digital transmission system SDH has become the dominant Transmission Mechanism of telecom networks. SDH-based transmission networks have gradually become the dominant direction of communication network construction. SDH is one of the most fundamental infrastructure for telecom carriers.

Advantages of SDH

SDH has three main features: Synchronous multiplexing, standard SDH optical interfaces, and powerful network management capabilities. To enable the program-controlled switch to transmit signals on the public network, the SDH optical interface provides a standard optical signal that is transmitted through optical fiber and interconnected with other terminals, so that the protocols of various terminals do not need to be unified. At the same time, due to the large network capacity, fast speed, and good performance of optical fiber communication, its low-cost communication and excellent bandwidth features are making it the main means of transmission for telecommunication networks.

Because a large number of electrical interfaces are replaced by an optical interface, the service information transmitted through SDH does not have to go through some intermediate back-to-back electrical interfaces of the conventional quasi-synchronous system, through the optical interface of the programmable switch, a large number of related circuit units and jumper optical cables are saved through the intermediate node, which improves the network availability and error code performance.

The SDH signal structure has taken into account the optimal performance of network transmission and switching applications. Therefore, it can be used for long-distance, relay, and access networks in various parts of the telecommunication network) it can provide simple, economic, and flexible signal interconnection and management, making the differences between different parts of the traditional telecom network gradually disappear, and the direct connection between them becomes very simple and effective.

Design and Implementation

Built-in SDH optical relay interface board (SDH optical interface board) provides STM-1 rate optical interface for switching equipment, which works in terminal multiplexing TM Mode and is used as a compact built-in SDH optical transmission system. It supports up to 63 up to 2 m businesses flexibly. All businesses are connected to the system's switching network through the 8MH-MVIP (HighDensityMulti-VendorIntegrationProtocol) bus.

Design principles

The sub-multiplexing structure in ITU-TG707 standard is used to realize the conversion from E1 link to STM-1 frame. SDH optical interface board is a digital relay processor and interface board. It is a seed processor attached to the main processor. In the system, multiple modules can be configured according to the requirements of the Internet and work independently. The SDH optical interface board provides the standard 155MSDH optical interface for the switching system and supports up to 63 2 m businesses of the Board. It provides the RS232 interface for debugging and provides a shared mailbox with the main processor, communication between the main processor and SDH optical interface board processor is realized.

The SDH optical interface board converts optical signals from optical fiber into 155 Mb/s differential signals after optical/electrical conversion by optical transceiver, then, Clock Recovery and data extraction, string/transform, scrambling code, segment overhead processing, B1, B2 computing, and high-end channel overhead processing are performed on the input signal. Then, the net load output of the VC-4 In the received signal is extracted from the Net Load of the VC-4 2 m Business signal, the frame processing and the cross adjustment of the 2 m link drive the back board. Similarly, the HMVIP signal from the back board is driven by the first 2 m link crossover adjustment, and then frame-based processing and ing to the VC-4, coupled with overhead byte, pointer processing, the optical transceiver Performs electrical/optical conversion and then sends it out.

Hardware Design

SDH optical interface board consists of eight modules: CPU and control module, shared mailbox module, photoelectric/electro-optic conversion module, and overhead pointer processing module, e1 ing, un ing, frame formation and link crossover network module, backplane drive circuit module, clock module, and power module.

CPU and control module: This module is composed of cpus. Its main function is to control the entire board. This module includes MC68360 high-end single-chip microcomputer), RS232 serial port), 29F040 (FLASH), HM628512FPRAM), MAX3064EPLD, ACEXEP1K30FPGA), 74HCT245 bus driver ).

Shared mailbox module: This module provides a 16 K dual-port RAM between the Board and MP as the shared mailbox.

Photoelectric/electro-optic conversion module: This module converts received optical signals into electrical signals to PM5342, and converts electrical signals from PM5342 to optical signals. Overhead pointer processing module: This module mainly includes the overhead of the regeneration segment of the STM-1, overhead of the multiplexing segment, the overhead of the higher-level channel, the overhead of the lower-level channel and the overhead of the higher-level and lower-level pointers.

E1 ing, un ing, frame formation, and link crossover network module: This module mainly completes ing, un ing, frame formation, and link crossover, that is, the flexible crossover between the business signal of 2 m that completes the ing/un ing and between the backplane link, and any selection of 2 m businesses from 63 to 2 m of a 155M.

Backplane driving circuit module: The backplane driving circuit is the interface circuit between SDH optical interface board and 04 switch. It isolates and drives the signal between the backplane and the current Board.

Clock module: The Clock module provides the 19.44M SDH clock function for this board. The clock is also the sending clock of the optical port of this board.

Power Supply Module: the power supply of the board comes from the 5 V of the back board, and the 3.3 V, V, and V chips are also used on the board, therefore, the function of the power supply module is to complete conversion from 5 V to 3.3 V, V, and V.

This Board is connected to the backboard using one 2mmA socket and one 2mmB socket, the backboard provides timing signal, control signal, address signal, data signal, Plate Position recognition signal, program loading link, + 5 V power supply and RS-232 serial port for the board. The Board provides 8 Mbit/s H-MVIP link for the backboard, A and B two external time points. To achieve communication between the Board and the host, a dual-port RAM is used as the shared mailbox.

Software Design

The software design adopts the assembly language of the 68K series single-chip microcomputer, which is mainly divided into two parts: ROM program design and RAM program design.

ROM Program

It initializes the CPU, including establishing channels for external communication, including serial ports and HDLC channels), detecting peripheral devices, and loading RAM programs. ROM programs are divided into Boot and debugging programs, the boot program is located in flash, used for board power reset. The system stack values SSP and PC values are automatically obtained from the 0 address when the 68360CPU is powered on, complete CPU initialization, ROM, RAM, DRAM testing, dedicated chip initialization, dedicated chip testing, HDLC loop testing, and print the test results to complete the boot function.

In addition, you can press the manual ABORT button on the board to enter the programming and operation environment TUTOR provided by 68K. In TUTOR, you can monitor/debug, compile/disassemble, and input programs, i/O Control and other functions. The starting address of the Single Board debugging program is $40000. Enter G40000 under the TUTOR to enter the debugging program.