Design FPGA from top to bottom

For IC design, the FPGA design hierarchy generally includes: system level and Behavior level, RTL level, gate level and transistor level. More generally, however, FPGAs are only used for real-time data acquisition control, certain fast processing algorithms, high-speed data channels such as PCIE\DDR3, and even some simple gluing logic, and FPGA development engineers do not have access to gate-and transistor-level. Top-down FPGA design method, according to the different roles, broadly summarized as follows.

1. system architects work at the system level, generally using high-level languages such as System C resources (Clock, Gtx\gtp,ip, core algorithm, determine Fpga selection, design module division. System-level design tools recommend the use of HDL Designer code. System-Level output includes: System design description and Function module division, Fpga Resource allocation, available Ip

2. Logic Design engineers work at RTL level, they use VERILOG\VHDL for functional module development, need to be accurate to the clock cycle, of course, you can also use the system Generator (Matlab) and the high-level integrated tools HLS (C language) development algorithms. The result output of the RTL level must be emulated correctly and the code can be synthesized. If conditions permit, post-simulation or board-level verification is required. RTL -level output includes: FPGA design documentation, integrated FPGA Design code ( not limited to VERILOG\VHDL, Systemgen or HLS design output), performance and resource analysis reports , validation methods and test results.

3. validation engineers work at the behavioral level, they validate the designed code, and the code is written primarily to generate incentives, most of which are more abstract, more efficient, and then examine the results. These codes are not implemented as specific hardware, and some do not need to be accurate to the clock cycle, just run in the simulation tool (Modelsim\isim\questa) . The output of the validation work includes: Validation method steps and code, validation reports, and so on.

4. The hardware test Engineer's task is to configure the FPGA for board-level testing, in the laboratory environment to build a test platform, the use of test instrumentation or test tooling to generate incentive conditions to verify that the test results meet the design requirements. The test engineer may not understand the FPGAat all, which requires the involvement of the relevant design engineer in the test documentation. The output of this phase includes the test steps and receiving standard documents, test reports, etc.

This is the top-down FPGA design method that I used in the project , when the manpower is enough, according to the well-defined design process can carry out the work methodically, reduce the mutual shirk responsibility between the project members, improve the work efficiency; Sometimes the resources are not enough, their body and several jobs, the task is heavy, but also enjoy themselves.

Design FPGA from top to bottom