Design of clock enabling Circuit

Clock enabling circuit is an important basic circuit for synchronous design. In many designs, although the processing speed of different internal modules is different, because these clocks are of the same source, they can be converted into a single clock circuit for processing. In FPGA design, the frequency division clock and the source clock skew are not easy to control, and it is difficult to ensure that the frequency division clock and the source clock are in the same phase. Therefore, we recommend that you use the clock enabling method to avoid clock "flying all over the sky" and avoid unnecessary sub-steady states, the design complexity is reduced while the design reliability is also improved.

We can use the D trigger with the enable end to implement the clock enabling function.

Clk1x is the clock generated after the four-division of CLK, clk1x_en is the clock enabling signal in the same frequency as clk1x, and clk1x_en is used as the DFF enabling end, d-end data can be pushed into the D Trigger only when the clk1x_en is effective, so that the Logic Functions of the circuit are consistent without introducing a new clock.

In a system, the former data input width is 8, and the latter data output width is 32. We need to convert 8-bit data into 32-bit data, therefore, the clock frequency of the later-level processing is 1/4 of the previous-level. If no clock is used, the former-level clock must be divided into four frequencies as the latter-level processing clock, this design method will introduce a new clock domain. To avoid this situation, we adopt the method at clock time to reduce the complexity of the design.

 

  Module  Gray
(
  Input CLK,
  Input  Rst_n,
  Input  [  7  :  0  ] Data_in,
  Output     Reg  [  31  :  0  ] Data_out,
 Output     Reg  Clk1x_en
);

  Reg  [  1  :  0  ] CNT;
  Reg  [  31  :  0  ] Shift_reg;

  Always @(  Posedge  CLK,  Negedge  Rst_n)
  Begin  
  If  (  !  Rst_n)
CNT  <=     2  '  B0;  
   Else  
CNT  <=  CNT  +  1  '  B1;  
  End   

  Always  @(  Posedge  CLK,  Negedge Rst_n)
  Begin  
  If  (  !  Rst_n)
Clk1x_en  <=     1  '  B0;  
    Else     If (CNT  =  2  '  B01)  
  Clk1x_en  <=     1  '  B1;  
    Else  
Clk1x_en  <=    1  '  B0;  
  End  

  Always  @(  Posedge  CLK,  Negedge  Rst_n)
  Begin  
  If  (  ! Rst_n)
Shift_reg  <=     32  '  B0;  
    Else  
Shift_reg  <=  {Shift_reg [  23  :  0  ], Data_in };
  End 

  Always  @(  Posedge  CLK,  Negedge  Rst_n)
  Begin  
  If  (  !  Rst_n)
Data_out  <=     32  ' B0;  
    Else     If  (Clk1x_en  =  1  '  B1) // The value of shift_reg is assigned to data_out only when clk1x_en is 1.  
  Data_out  <=  Shift_reg;
  End   

 Endmodule