Design of Camera link standard interface for image acquisition system

The high-speed data acquisition system can transmit and process real-time images captured by the camera, and realize the communication between video capture card and computer. The interface of the system connection camera is using Camera link interface, through the camera link interface, the real-time image is transmitted to the FPGA Image acquisition card for real-time processing, and the communication between the acquisition card and the computer is realized through the PCI interface. This paper mainly studies data acquisition system Cam-era link Interface technology.

Camera link is a special interface standard for digital camera data transmission, which was launched in October 2000 by a number of camera vendors and image capture companies. The camera link standard simplifies the connection between the computer and the camera. This design selects Dalsa company's DS-21-02M30 camera, which supports the camera link interface. The camera data is transferred to a fpgastratixii of Altera company via the camera link interface for processing. In FPGA, the data cache can be used in FPGA to design various image processing programs for real-time image processing.

1 DS-21-02M30 Camera Introduction

The DS-21-02M30 camera provides a highly sensitive 8/10-bit image. To achieve excellent resolution and grayscale at the same time, the DS-21-02M30 camera image has a resolution of 1 600x1 200 and a pixel size of 7. 4μmx7. 4μm, the pixel data output clock is 60 MHz and the maximum frame rate is up to/s. By setting the pixel data Format command, you can set the pixel data to 8-bit, 10-bit. The power supply voltage is 12~25 V, which is less than W.

By sending an ASCII control command and a diagnostic command to the DS-21-02M30 camera via an asynchronous serial port, you can control the gain, compensation, frame rate, exposure time, exposure mode, and output of the test image of the camera output image, as well as diagnose the camera. Serial protocol: 1 bit start bit, 8 bit data bit, no parity bit, 1 bit stop bit, communication baud rate is 9 bps (camera default), by setting the baud rate command it can be set to the five bps, the five bps and the three bps.

The DS-21-02M30 camera has 4 exposure modes, and you can select the appropriate exposure mode for the camera by setting the exposure mode command.

Mode 2: Internal trigger mode (default exposure mode for the camera). The frame rate and exposure time can be controlled by the corresponding command.

Mode 3: External trigger mode for maximum exposure time.

Mode 4: External trigger mode. The frame rate and exposure time are controlled by an external trigger signal, i.e. the high stage of the external trigger signal is the exposure time, and the frequency of the external trigger signal is the frame frequency.

Mode 6: External trigger control frame frequency, exposure time can be controlled by the corresponding internal command.

DS-21-02M30 camera commands are issued in ASCII format.

Send. When you send a command to the camera, it ends with a carriage return. After the camera is power on, the light behind the camera flashes and is sent through the serial port "camerainitialization in Process,please Wait ... Ok> "String. When the "Ok>" string is received, it indicates that the camera will start transmitting the image data, and the LED on the camera is no longer flashing. When the camera receives a valid command, the "ok>" string is returned as an answer, otherwise the "Error x:error massage>" string is returned as the answer. where x is the error designator, error massage indicates a specific description of the error. The camera's answer string is signed with the symbol ">" as the Terminator.

2 Camera link structure and principle

Camera link is a special interface standard for digital camera data transmission, an image data, video data control signal and a bus interface for camera control signal transmission for digital cameras, with data rates up to 2. -Gbps. This standard specifies the interface mode, camera signal, port configuration, image data bit configuration, connector pin definition and connection line, standard receiver chipset. With this standard, the digital video camera data interface output with fewer lines, the connection cable easier to manufacture, more universal, and the data transmission distance than the normal transmission way farther. The main feature is the use of LVDS (low voltagedifferential signaling, differential signal) technology, so that the data transmission rate of the camera greatly improved.

Prior to the advent of the Careera link standard, the industry had some standards (such as the more popular IEEE-1394: interface) as a technical standard for data transmission. IEEE-1394 is widely used in many fields, such as digital cameras, cameras and other digital imaging fields. The IEEE-1394 interface features low-cost, fast, hot-swappable, data transmission rates that can be extended, and standard open. However, with the increase of digital image acquisition speed and the increase of data volume, the original standard can not meet the demand. In order to simplify the connection of data, achieve high-speed, high-precision, flexible, simple connection, on the basis of the channel link bus technology developed by Nationalsemiconductor Company, the camera link standard has been developed jointly by many cameras manufacturers. Camera link based digital camera acquisition speed and data volume are better than based on the IEEE-1394 standard.

Camera link is a planar display solution based on the physical layer of LVDS. Figure 1 is the connection block diagram of the camera link bus and the receiving end, is also the basic mode of the bus. The bus sends the 28-bit parallel data to 4 pairs of LVDS serial differential data, and a pair of LVDS serial differential data lines are used to transmit the image data output synchronous clock, while the bus receiving end converts the serial differential data into 28-bit parallel data while simultaneously converting the synchronous clock. This not only reduces the usage of the transmission line, but also reduces the electromagnetic interference during transmission due to the use of serial differential transmission.

3 High speed Data acquisition card Camera link Interface design

The basic block diagram of the high-speed data acquisition system is 2. The FPGA sends a control signal to the camera, the data in the camera is transmitted to the image Acquisition card via the Careera link interface, and the data is read into the FPGA, and the SDRAM is in slow existence. It can realize high-speed image processing according to the user's requirement in FPGA, according to the result of image processing, the user's required control can be completed by FPGA. The Image acquisition card is connected with the computer through the PCI interface, the computer can configure the Image acquisition card and the camera, and the computer can obtain the image processing data from the acquisition card. Next, the camera link interface technology between FPGA and camera is studied in detail.

3. 1 Camera Link Interface for DS-21-02M30 cameras

The Camela link Bus standard stipulates that, in full mode, up to 8 ports (port A~port H) can be used to transmit data, with 8-bit data per port. DS-21-02M30 Camera uses port A~port C port, which is the basic mode (base). The camera backend has a MDR26 connector, which corresponds to 8-bit data for a, B, and C three ports, plus fval, Lval, Dval, and SP four-bit data control signals, and a total of 28 bits of parallel data bits.

3. 2 hardware design of the Camera link interface

The hardware connection for Camera link is shown in block Diagram 3. The hardware circuit comprises 3 parts: the camera connects the image Acquisition card via the MDR26, the LVDS signal and the CMOS signal conversion circuit of the Cameralink interface, the FPGA receives the camera data and the transmit control part.

In order to control the external triggering of the camera and send commands to the camera, the four-channel CMOS signal is converted to the core of the LVDS differential signal. ds90lv047, as an image grabber, sends an external sync trigger signal and a conversion command to the camera. Since the DS-21-02M30 camera uses only the CC1,FPGA image capture card, the control of the camera is achieved through CC1 and SERTC signals. In order to receive the response string sent by the camera to the image processing system, the ds90lv048 chip is chosen as the receiver of the image processing system. The ds90lv048 chip is a driver that converts a four-channel LVDS differential signal to a CMOS signal.

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Camera link standard interface design for image Acquisition system