Design of divider based on Verilog (the principle of odd-even frequency division and its circuit implementation: UP)

In a digital system, a clock pulse of multiple frequencies is often required as the driving source, which requires the frequency of the FPGA's system clock (too high) to be divided. The frequency divider is divided into odd frequency, even frequency, half-integer and fractional, in the FPGA system where the clock is not very strict, the frequency divider is usually realized by the counter loop.

Even divide: Assuming n-frequency, by the clock to be divided by the counter count, when the counter from 0 to n/2-1, the output clock to flip, and give the counter a reset signal, so that the next clock from the zero start counting. to cycle down. This method can achieve arbitrary even frequency division. , two D flip-flop cascade to achieve four-way circuit, principle: to a clock pulse, D-end data is sent to the output Q, while outputting a reverse data to the Q non-end, the next clock pulse to, repeat the above process, but the data has been reversed, thus every two clocks, Q number is reversed once, thus getting two parts frequency, Then get the four divide.

How the TIPS:D trigger works (verifies that its state is the same, assuming that the initial value is 0 or 1, based on the logical relationship analysis)

For a divider with a crossover factor of 10, this example input clock system 50M clock (clk_50m), the output is a very frequency clock (f_50). Set a 3-bit counter, when the timing register to 4 (10/2-1), the output divider signal is reversed to obtain a 10-divided output. Function simulation and timing simulation (latency), respectively

Modulefengping_2 (clk_50m,f_10);inputclk_50m;//system input clock, 50M, cycle 20nsOutputf_10;//10 frequency output, 5MRegf_10;//Output RegistersReg[2:0] CNT;//Count Registers always@(Posedgeclk_50m)//the rising edge of each clock cycle is triggered,//executing the statements in Begin_endbeginif(cnt==3'B100)//To determine whether CNT is 4, is the case to execute the following procedurebeginf_10<=~f_10;//Take the f_10 back .cnt<=3'B0; Count Register Clear 0EndElse //CNT not to 4, execute the following procedurebeginCNT<=cnt+3'b1;//count Register self plus OneEndEndEndmodule

Odd divide: First, completely can be achieved through the counter, such as three-way, through the clock rising along the trigger counter to the three-count, when the counter count to the adjacent value two flips, such as can be counted to 1 o'clock, the output clock is flipped, counting to 2 o'clock again to flip. That is, the count value is flipped two times in the adjacent 1 and 2. This achieves a three-way duty ratio of 1/3 or 2/3. If you want to achieve a duty ratio of 50% of the three-way clock, you can be divided by the clock falling along the trigger count, and the rise along the same method Count three, and then the fall along the resulting three-frequency clock and the rising edge of the clock generated by the phase or operation, you can get a duty ratio of 50% three-way clock. This method can achieve arbitrary odd frequency. Classified as the general method is: for the implementation of the duty ratio of 50% N-odd frequency division, first the rising edge triggered by the modulo N count, the count is selected to a certain value for the output clock rollover, and then after (N-1)/2 flip again to get a duty ratio of non-50% odd N-frequency clock. Furthermore, when the modulo N count is triggered at the same time, and the output clock flips at the same value as the rising edge of the trigger clock to flip the selected value, the output clock is flipped again (N-1)/2, and an odd-N clock that generates a duty ratio of 50% is flipped again. The two duty cycles are not 50% of the N-divided clock phase or operation, resulting in a duty ratio of 50% odd-n clock.

ModuleFenpin (inputI_CLK,inputI_rst_n,OutputO_CLK); //log2 (3) = 1.5850 <= 2Reg[1:0] Cnt_p;//Rising Edge Count Sub//3-bit rising edge counter: 0 ~ 2 always@ (PosedgeI_CLK,Negedgei_rst_n)begin  if(!i_rst_n) cnt_p<=0; Else    begin    if(Cnt_p = =2)//2=3-1Cnt_p <=0; Elsecnt_p<= cnt_p +1'B1;    EndEnd //log2 (3) = 1.5850 <= 2Reg[1:0] Cnt_n;//Falling Edge Count Sub//3-bit falling edge counter: 0 ~ 2//2 = 3-1 always@ (NegedgeI_CLK,Negedgei_rst_n)begin  if(!i_rst_n) Cnt_n<=0; Else  begin    if(Cnt_n = =2)//2=3-1Cnt_n <=0; ElseCnt_n<= Cnt_n +1'B1;  EndEnd   Rego_clk_p;//rising edge Clock output register//output rising edge clock//0 ~ 1↑-> 1//(+) ~ 2↑-> 0//1 = 3>>1//2 = 3-1 always@ (PosedgeI_CLK,Negedgei_rst_n)begin  if(!i_rst_n) o_clk_p<=0; Else  begin    if(Cnt_p <=1)//1 = 3>>1, shift right is equivalent to dividing by 2O_clk_p <=1; Elseo_clk_p<=0; EndEnd  RegO_clk_n;//falling edge clock output register//Output falling Edge clock//0 ~ 1↓-> 1//(+) ~ 2↓-> 0//1 = 3>>1//2 = 3-1 always@ (NegedgeI_CLK,Negedgei_rst_n)begin  if(!i_rst_n) O_clk_n<=0; Else  begin    if(Cnt_n <=1)//1 = 3>>1O_clk_n <=1; ElseO_clk_n<=0; EndEnd AssignO_CLK = o_clk_n & o_clk_p;//bitwise with (function: mask)  Endmodule

The second method: for the odd number of times the n-frequency clock, the first N/2 division (with a decimal, that is equal to (n-1)/2+0.5), and then two-way to get. The ratio of the duty to 50% odd multiples is obtained. Here's how to design a fractional divide.

Fractional divide: First of all, how to do n+0.5 division, this crossover needs to operate the input clock. Basic design idea: for the n+0.5 frequency division, the first modulo n count, in the count to n-1, the output clock is assigned as ' 1 ', Back to Count 0 o'clock, also assigned to 0, so you can know that when the count value is n-1, the output clock is 1, so as long as the count value n-1 is half the input clock period, that is, the implementation of the n+0.5 divider clock, so it is a difficulty to maintain the n-1 half clock cycle. It can be found that because the counter is counted by the rising edge of the clock, it is possible to flip the count trigger clock when the count is n-1, and the falling edge of the clock becomes the rising edge. That is, when the count value is n-1, the clock falling edge becomes the rising edge, then the count value n-1 only half the clock cycle, since the clock rollover falling edge becomes the rising edge, so the count value becomes 0. Therefore, each time a n+0.5-frequency clock is generated, the trigger clock is to be flipped once.

Design of divider based on Verilog (the principle of odd-even frequency division and its circuit implementation: UP)