Design of FPGA-based 160-Channel Data Acquisition System

FPGA-based 160-Channel Data Collection System Design Time: 09:50:21 Source: foreign electronic components Author: Wang yongshui, Ren Yongfeng, Jiao xinquan

L Introduction

With the development of science and technology and the national economy, the demand for electric energy is increasing, and the demand for power quality is also increasing. This poses a challenge to power quality monitoring. The monitoring of power quality usually requires multi-channel data collection.
Because of its large coverage, strong periodicity, and large amount of data collected, a high requirement on the collection, transmission speed and accuracy of the data collection system is put forward. Commonly used data collection solutions often use single-chip microcomputer or digital mail
Number processor (DSP) as the controller. To control the operation of ADC, memory, and other peripheral circuits. However, it is difficult to achieve multi-channel high-speed because of the single-chip microcomputer's instruction cycle and processing speed.
Data collection system requirements, although DSP can achieve high-speed data collection, but while improving its speed, it also increases the system cost. Field programmable gate array (FPGA) with high clock frequency, internal
Low latency, fast speed, high efficiency, flexible composition, and other features have the advantages of single-chip microcomputer and DSP in high-speed data collection.

2 Multi-Channel Signal Acquisition Principle
Figure 1 shows the hardware structure of a multi-channel high-speed data collection system. The 160-channel signal goes through the low-pass filter and the output follower to the multi-channel analog switch, and the FPGA control logic selects the analog switch. Only one channel is selected at A time, which is converted to A/D and then stored in the memory.

3. Connection Between the switch and FPGA control logic
Figure
In 2a, ADG506 is a switch that can select a 16-channel signal. 10 pieces of ADG506 are used in the system. The enable end of ADG506 is controlled through FPGA to realize switching. ADG506
The 18-pin is the enable end, which is effective at a high level. Use ENl ~ in Figure 2b ~ ENl0 control can be used to select 10 pieces of ADG506; A0 ~ A3 encoding enables signal selection. A0 ~ A3
The value of S16 is selected at 0000, and so on, and S16 is selected at 1111. The system clock is 40 MHz and the sampling rate is 500.
KHz, each signal collects 10 points, a total of 160 channels. A0 ~ A3 depends on the 4-bit lower of f_channel; ENl ~ ENl0 depends on the other digits of f_channel.
Figure 3 shows the program flowchart.

4 Time Calculation
The electronic switch used in the sampling system has a contact resistance of about 400 Ω, a shutdown resistance greater than 1 kb, a pin integrated capacitor of 30 pF, and an operational amplifier of AD824, the input impedance is greater than 1013 Ω. The Charging Process of the capacitor is as follows:

Capacitor leakage process:

Because there are a total of 192 follow-up circuits, the condition t2 ≥192t1 is true. Formula (2) and formula (4) are constraints for on-and off-switches. When the ripple coefficient is 1 ‰, there is exp (
T1/1.2X10-8) ≤ 0.001, exp (A t2/300) ≥ 0.999, so tl ≥ 82.9 ns and t2 ≤ 300
Ms. Obviously, the limit l and t2 do not meet the constraints t2 ≥192t1, so one round of switch switching cannot satisfy both the formula (2) and formula (4 ). In order to improve accuracy, t2 <300
MS to meet formula (4) conditions. T1 = 1.56 ms. In order to satisfy the formula (2), the Ui must be small enough. After calculation
The millisecond-time capacitor can be charged as high as 100%.
In short, the requirements are as follows: ① The switch switching speed is no less than 192/t2 ≈ 640Hz; ② the switch time must be greater than 192x82.9 ns = 15.92 μs regardless of the switching speed, the ripple is smaller than 1‰. ③ the sampling rate of the sampling system is 500 Ks/s.

5 conclusion
By
FPGA is used for the control of the entire system, which is flexible in the organization mode. The internal configuration of FPGA can be modified and debugged based on the actual situation on the site. This data collection system is applicable to a variety
Data collection is an ideal real-time data collection solution. This design has been used in the signal acquisition system of a device. The actual application proves that the collection system fully meets the needs of multi-channel data collection.
. The typical single-channel A/D acquisition system is improved in A data acquisition system that simulates switch cascade. The input capacitance of the/D converter is the integrated capacitance of multiple switches, and its capacitance value is small. This improvement solution
This improves the speed and accuracy of data collection.