Design of ixp425 PCI driver in uboot

Abstract:
This paper describes the ixp425 PCI Controller structure and operation method, and then explains how to write the PCI driver for ixp425 in uboot, and finally explains how to drive the EEPRO-100 of PCI Nic.

Introduction
Uboot is an open-source project under SourceForge. It is short for universal bootloader, that is, the general-purpose Startup Program. By selecting different compilation options, you can boot multiple processors, such as PowerPC, arm, MIPS, and x86.
Ixp425 is an Intel-based CPU that uses XScale cores. It has three internal network processing engines and is widely used in network devices. To use a network processing engine, you must use the libraries provided by Intel. However, for copyright reasons, uboot does not provide support for the network processing engine.

You cannot use a network. To facilitate debugging, we have compiled a PCI driver for uboot so that you can use the PCI Nic to access the network.
This article describes how to write the PCI driver ixp425, and take the EEPRO-100 Nic as an example, describes how to drive the PCI Nic.

2. PCI configuration space
Each pc I device has three types of physical space: configuration space, memory space, and I/O space. The configuration space is a continuous space of 256 bytes. The first 64 bytes are headers and the remaining 192 bytes are device-related information. In the 64-byte header, the definition of the first 16 bytes is definite. the specific meaning of the last 48 bytes varies with the device. Figure 1 shows the header area of the configuration space.

Figure 1
An important part of the configuration space is the base address register, which maps the address space of the PCI device to the starting physical address of the system address space. Here, bit0 = 1 indicates I/O space ing, and bit0 = 0 indicates memory space ing. All pc I devices must map memory space or I/O space. Write full 1 to the bar and then read the relevant registers to determine the size of the required address space.

Tri-ixp425 PCI Controller
Ixp425 is integrated with the PCI Controller, which supports both master and slave modes. The specific working mode can be read from the bit0 of the PCI control status register, when the system restarts, this bit is set by bit1 of the extended bus and is read-only. If this bit is 1, ixp425 is used as the master device. If this bit is 0

Then, the ixp425-bit slave device.
In ixp425, PCI registers can be divided into two types. One class can be directly accessed by the AHB Bus Inside ixp425, and the memory can be uniformly configured. It provides interfaces to access the PCI configuration space. Another type of registers is the PCI configuration space registers, which comply with the PCI bus standard and are described in section 2.
3.1 configuration method
For the PCI configuration space of ixp425 and the PCI configuration space of external devices, the access method is different.
A. Access the configuration space of ixp425.
The PCI configuration space in ixp425 cannot be accessed by the AHB Bus. ixp425 provides the pci_crp_ad_cbe, pci_crp_wdata, and pci_crp_rdata registers to access the internal PCI configuration space. Pci_crp_ad_cbe records the address and command to be accessed, pci_crp_wdata,

Pci_crp_rdata is the Data Writing register and Data Reading register respectively. The access process is as follows:
1. Write the command to be operated and the offset to access the register in pci_crp_ad_cbe.
2. To write data to pci_crp_wdata, read data from pci_crp_rdata.

B. Access the PCI configuration space of an external device.
Pci_np_ad, pci_np_cbe, pci_np_wdata, and pci_np_rdata. These four registers are a set of non_pre_fetch registers that provide access to the external PCI configuration space. They belong to the first type of registers described above and can be directly accessed by the AHB Bus. Their addresses are 0xc0000000, 0xc0000004, 0xc0000008, and 0xc000000c. Pci_np_ad is a pci bus address register that provides an address to access the external PCI configuration space. Pci_np_cbe is a PCI command and byte control register. It performs operations on the external PCI space, including read/write configuration space, the read/write memory space and read/write I/O space are mainly used to read and write the configuration space during the configuration process, memory space and I/O space can be read and written by the CPU after the configuration is complete. Pci_np_wdata and pci_np_rdata are the data to be read or written, which will be saved in

Two registers. Access to the external PCI space can be divided into the following three steps:
1. Write the address to access the register in pci_np_ad. The format is 2:

Figure 2
The PCI bus can work in modes 0 and 1, but ixp425 only works in Mode 0. Therefore, only operations in Mode 0 are described here. It should be pointed out that the id_sel pin needs to be set to a high level when selecting a specific PCI device. Its function is like a chip selection signal. The high level selection can be completed at 11 to 31 bits of pci_np_ad, if the address line is 31 bits connected to the id_sel pin of the external device, the 31st position is 1.
2. Write the command to be operated in pci_np_cbe
3. If you want to write data, write data in pci_np_wdata. If you want to read data, you can read it in pci_np_rdata.
3.2 conversion between AHB address and PCI address
When performing memory read/write and I/O read/write, you can use address translation bursts. The following describes the Conversion Relationship Between the AHB address and the PCI address.
Conversion from a AHB space to PCI Space
In ixp425, the PCI address space is divided into four windows, a total of 64 m, as shown in table 1:
Start address and end address
Window 1 (16 Mb) 0x48000000 0x48ffffff
Window 2 (16 Mb) 0x49000000 0x49ffffff
Window 3 (16 Mb) 0x4a000000 0x4affffff
Window four (16 Mb) 0x4b000000 0x4bffffff
Table 1
When the address on the AHB Bus is like an address, it will be converted through the pci_pcimembase register. This register is divided into four parts, each of which records the converted base address. For example, if the value of pci_pcimembase is 0x12345678 and the AHB Bus address is 0x48012345, the converted PCI address is 0x12012345. If the AHB Bus address is 0x4a005678, the pci bus address is 0x56005678.
Conversion from B PCI address to AHB address
The conversion from PCI address to AHB address is controlled by pci_ahbmembase, pci_ahbiobase, and several registers of the BAR0-5 in the configuration space. Registers pci_ahbmembase are divided into four parts, corresponding to the BAR0-3 four base address registers, responsible for PCI memory Cycle address conversion. Assume that the value of pci_ahbmembase is 0x01020304, bar0 is 0x20000000, bar1 is 0x21000000, bar2 is 0x22000000, and bar3 is 0x23000000. When the pci bus address is 0x21001234, It is mapped to bar1, and the corresponding AHB address is 0x02001234.
The registers pci_ahbiobase correspond to bar5. pci_ahbiobase records the base address of I/O on the AHB Bus, while bar5 records the base address on the PCI bus, their conversion methods are the same as those of the above memory address. The address falling within the bar4 range will be directly converted to a register PCI doorbell register in ixp425.

4. PCI driver
4.1 PCI Controller Initialization
Since ixp425 in the target board ixdp425 works in the master mode, only the initialization process in the master mode is described here. The process is as follows:
1. Assign pins to the PCI Controller. In addition to the connection to the PCI Controller itself, ixp425 also uses some gpio pins, including gpio14 clock pins, gpio13 reset pins, and GPIO8-11 interrupt pins.
2. Configure the registers pci_ahbmembase, pci_ahbiobase, pci_pcimembase, and the base address register of ixp425 to initialize the conversion between AHB and PCI addresses in ixp425.
3. Scan external devices. The PCI device is detected by scanning on the PCI bus. If a device ID is read on the bus, it indicates that a device exists. In this case, you should also read the base address register of the device, to determine the memory size of the device.
4. assign a base address to each device. The size of the scanned memory is the base address on the unified AHB Bus calculated by the peripheral device, and the calculated base address is written to the base address register of the corresponding PCI device.
4.2 connect to the NIC Driver
A U-BOOT driver has been provided in the EEPRO-100 and can be used as long as it is connected to a PCI driver.
1. Add the compilation option. Add # define config_eepro100 to include/configs/ixdp0000.h, so that the U-BOOT will add the program part of the NIC during compilation.
2. Connect to the NIC Driver. Two macros are used in the driver of the NIC to convert the AHB address and the PCI address. bus_to_phys (a) provides the conversion from the PCI address to the AHB address, phys_to_bus () converts an AHB address to a PCI address. The two macros internally use a structure to represent the value of the Register described in section 3. The structure is as follows:
Struct pci_region {
Unsigned long bus_start;/* start on the bus */
Unsigned long phys_start;/* start in physical address space */
Unsigned long size;/* size */
Unsigned long flags;/* Resource flags */
};
The starting address of the PCI address, starting address of the AHB address, memory size and resource type (memory or I/O) are defined in the structure. Assign a value to this structure during initialization, and then call the pci_register_hose (hose) function; register with the system to connect the NIC Driver.

Conclusion 5
This article introduces how to add the PCI driver to the ixp425 under the U-BOOT, explains how the ixp425 PCI Controller works, and finally explains how to add the PCI Nic EEPRO-100 to the U-BOOT.
Here, it basically works (PCI interface). When ixp455 wants to access the mar0 of rtl8139, it is in the range of 0x08. Then the software only needs to read 0x48000008 and convert it to 0xc1000008 on PCI, while the bar of rtl8139 is 0xc000000. to translate the base address, it finally accesses the 0x8 and mar0 registers.

So far, all the PCI transmission channels have been connected. The following describes the PCI interruption and DMA transmission data.

Referenced in "casual BBS" "2 beanet": www.2beanet.com/bbs http://www.2beanet.com/