Design of tft LCD Driver Based on Blackfin Processor

Http://www.ic37.com/htm_tech/2009-10/70649_597020.htm

 

0. Preface for a long time, traditional handheld devices, such as PDAs, are generally monochrome LCD Devices Due to hardware restrictions, and the user interface is very simple. With the popularization of high-performance embedded processors and the decreasing of hardware costs, embedded systems become more and more powerful. Driven by multimedia applications, color LCD is applied to embedded systems. The new-generation handheld computers (PDAs) mostly use tft LCD display devices that support graphic interfaces, image display, and video media playback. The operating systems of PDAs include Windows CE and palmos. Where
Linux has a low core, low cost, and open source code, making it an operating system that has been developed by various vendors. This article discusses two tft LCD Driver schemes based on the Blackfin embedded processor.

1. Introduction to Blackfin Processor and tft LCD Blackfin series processor is the first embedded processor developed by ADI. It integrates the advantages of microcontroller, DSP and media processor into a single architecture, it has been widely used in consumer multimedia, network communication, and other fields.

Bf531 is a Blackfin Processor with a maximum clock frequency of 400 MHz. It has two 16-bit Mac, two 40-bit ALU, four 8-bit video ALU, and one 40-bit shift. It has up to 148 Kbytes in-chip memory and two dual-channel memory DMA controllers. The system peripherals include a UART port, an SPI port, and two serial ports (sports ), four universal clock timers (three With PWM function), one real-time clock, One watchdog clock timer, and one parallel peripheral interface.

We use fg050605 as our design screen. This LCD screen is 5.6 inch, with 960 (w) x 234 (h) pixels, each three pixels at a point, that is, there are 320 vertices in each row, and 234 rows in total. This line is very simple: a total of 32 pins, one data clock, one line frequency, one field frequency, one data enabling, a total of 18 data lines in three colors, the remaining are empty feet and power cords.

LCD sequence 1 is shown in the following figure:

Figure 1: three real-color LCD Driver schemes: DSP-based LCD driver, DSP-based embedded uClinux LCD driver, and FPGA-based LCD driver. This article focuses on the implementation of the first two solutions.

2. The system design consists of 20 pins in the PPI port of the Blackfin Processor. Each clock cycle can send and receive 16-bit data. It provides a seamless data transmission interface for tft LCD.

The pixel clock frequency of this LCD screen is 6.25 MHz, and FPGA is used for Division. The clock is connected to the ppi_clk pin at the same time. The frequency is 408 pixel clock cycles, and the field frequency is 59Hz, that is, 259 frequency cycles, respectively connected to the Blackfin Processor's tmr1 ⁄ ppi_fs1 and tmr2 ⁄ ppi_fs2 ports.

In the design, we use a 16-bit color display mode. Therefore, we connect the highest bits in red and green with the lowest bits, that is, R0, R5, B0, and B5. The 16 data lines are connected to the ppi0 to ppi15 ports of the Blackfin Processor respectively. The data enable pin is connected to FPGA. The hardware Diagram 2 is shown below:

 

2: hardware block diagram 3. Like traditional DSPs, hardware-based LCD drivers are directly based on Blackfin processors.

The DMA method is used to transmit color data through the PPI port. The data to be displayed is stored in the two cache areas of the SDRAM. the ping-pong mode is used to write data to a storage area, read from another storage area. We set a non-cache storage area in the SDRAM. Because each vertex is represented by 16 bit data, the two cache areas are 320 (234 + 9 + 16) 16 bit in total, 9 + 16 indicates the number of lines lost in each signal.

In the initialization of 3.1 DMA, we first configure the DMA parameters. Here, DMA uses the descriptor list (small model) and 2D transmission mode to transmit data of one word each time. First, set an address list to load the first addresses of the two cache regions. In this way, DMA transfers the data read from the Space indicated by the address to the PPI port. Set DMA to transmit 259 rows per game, and transmit 320 words per line. Finally, configure dma0_congfig and enable DMA. The main settings are descriptor.
List, inner loop count of 2D DMA, set the increment of the read address of the next 2D DMA to the local address, outer loop count of 2D DMA, and configure the DMA working mode.

The initial PPI of 3.2 PPI has two working modes: ITU-R 656 and general-purpose PPI. Because we only need to send data through the PPI port, the GP mode is used. Set the valid descent edges of ppi_fs1 and ppi_fs2 to transmit 16-bit data at a time, externally triggered, and synchronous signals of two external frames. You must configure the PPI parameter, the latency from when the field frequency signal is sent to the start of data transmission, and the number of data transmitted per line.

3.3 timer initialization because we use two external frame synchronization signals, we use tmr1 ⁄ ppi_fs1 as the line frequency signal (hsync), tmr2 ⁄ ppi_fs2 as the Field Frequency Signal (vsync ). In order to debug the program, we configure the timer as a simulation when the timer continues to work. Because only the data is sent to the LCD, we configure it as pwm_out mode. Our timer uses ppi_clk, so we still need to set it as the pwm_out clock and count to the end of the cycle. The cycle and pulse width of timer1 and timer2 are set according to the LCD hardware manual.

3.4 frambuffer initialization, the LCD configuration has been basically completed, we write data on the screen to write data in the two data buffers. However, it should be noted that after each incoming field frequency signal, 19 rows of data will not be displayed on the screen, followed by 234 rows of screen display, the last six rows of data are redundant data to be discarded. Therefore, we need to write all the color information of the displayed data in the middle 234 rows. When initializing framebuffer, you should first write the 19 lines of content to be discarded, then write the initialization color data of the 234 lines, and finally initialize the data lost in the last 6 lines.

4. the uClinux-based LCD-driven embedded system is application-centric, dedicated computer systems that are based on computer technology and can be tailored to software and hardware, and adapt to the functional, reliability, cost, volume, and power consumption requirements of application systems. UClinux is designed for Embedded Systems with no memory management unit (MMU) as the target processor. It is an excellent embedded Linux version, it has been successfully transplanted to many platforms. For developers
The combination of the Blackfin Processor and uClinux is very attractive.

On the site of blackfin.uclinux.org, we provide support for embedding uClinux on Blackfin. This design uses its embedded software support. The uClinux-dist-R06R2-RC2.tar.bz2 is selected as the source code of uClinux, And the uCLinux embedded platform is transplanted successfully. We use the source file root directory uClinux-Dist/linux2.6.x/driver/Video/bf537-lq035.c
As a template to modify the LCD driver.

4.1 program file modification to the bf537-lq035.c as a template to modify the bf533-fg0506.c, because the source program is compiled by the bf537 Development Board, we focus on modifying the signal using port, and LCD settings. Because our LCD backlight is subject to inverter adjustment, the backlight brightness adjustment and related options in the original program file will be blocked. Key Modification points: liquid crystal field frequency, clock, screen size, timer settings (timer1.timer2), various register settings, and write data
DMA and PPI procedures. LCD data: the number of lines to be dropped after the arrival of the field frequency signal, the total number of lines to be dropped for each signal, and the Field Frequency ppi_clk clock part: if you configure PPI, HDP, and hpw, the PPI does not transmit data during this period. Configure Timer: Enable the clock and set the timer parameters. Set DMA parameters, screen size and color, and initialize framebuffer.

4.2 makefile rewrite this part is to compile the newly written LCD driver into the target file during kernel compilation. Add the compilation rules in uClinux-Dist/linux2.6.x/driver/Video/makefile.

4.3 modify menu "graphics support" to enable the LCD driver to be compiled when the uClinux kernel is compiled. Add the compilation information in the uClinux-Dist/linux2.6.x/driver/Video/kconfig file. In this way, when you use make xconfig to compile the system kernel, you can select this option in graphic support under the device driver of the custom kernel settings.

5. Conclusion After debugging and modification, the LCD of the final two schemes can correctly and stably display the required data, which can meet the expected data display requirements of this design. At the same time, because TFT liquid crystal has a wide visual angle and rich 16-bit color performance, the LCD display is designed to achieve the desired effect, and has a certain significance for the screen display technology of embedded devices.

Innovation point of this article: through the rational use of the internal resources of the Blackfin embedded processor, it is combined with the embedded system uClinux and applied to the driver design of tft LCD. Compared with the hardware-based drive design, the drive design based on the embedded system uClinux has the advantages of strong functionality, high reliability, low cost, small size, low power consumption, and more practical application value.