Design techniques for reducing FPGA Power Consumption

Use these design techniques and ISE function analysis tools to control power consumption

The new generation of FPGA is getting faster and faster, with higher density and more logic resources. So how can we ensure that the power consumption does not increase along with this? Many design choices can affect the power consumption of the system, from explicit device selection to small frequency-based state machine value selection.

In order to better understand why the design skills discussed in this article can save power consumption, we will give a brief introduction to power consumption.

Power Consumption includes two factors: Dynamic Power Consumption and static power consumption. Dynamic Power Consumption refers to the power consumption required to charge and discharge the capacitive load in the device. It depends largely on the frequency, voltage, and load. Each of these three variables is under your control.

Dynamic Power Consumption = capacitor x voltage 2 x frequency

Static power consumption refers to the sum of power consumption caused by leakage current of all transistors in the device (source pole to drain pole and gate leakage, often concentrated as static current) and any other constant power consumption requirements. The leakage current depends largely on the junction temperature and transistor size.
Constant power consumption requirements include current leakage caused by the final connection (such as the pulling resistance. There are not many measures to influence leakage, but constant power consumption can be controlled.

Consider power consumption as soon as possible

The power consumption decisions you make in the early stages of the design have the greatest impact. Deciding which component to use is of great significance to power consumption, while inserting a bufgmux on the clock has little impact. The sooner the power consumption is considered, the better.

Appropriate components

Not all components share the same static power consumption. According to the general rules, the smaller the technical size of the device, the larger the leakage power consumption. However, not all technologies are the same. For example, for 90 nm technology, there is a significant difference in static power consumption between Virtex-4 devices and other 90 nm FPGA technologies,
However, the static power consumption increases with the reduction of the process technology, while the dynamic power consumption decreases, because the smaller process has lower voltage and capacitance. Consider which power consumption has a greater impact on your design-standby (static) power consumption or dynamic power consumption.

All Xilinx devices have specialized logic except General slicing logic units. It includes block ram, 18 × 18 multiplier, dsp48, srl16s, and other logic. This is not only because specialized logic has higher performance, but also because it has lower density, so it can consume less power for the same operation. When evaluating your device options, consider the type and quantity of specialized logic.

Selecting appropriate I/O standards can also save power consumption. These are simple decisions, such as selecting the lowest driving strength or a lower voltage standard. When high-power I/O standards are required for system speed, a default state is planned to reduce power consumption. Some I/O standards (such as GTL/+) need to use an upstream resistor to work normally. Therefore, if the default status of the I/O is high rather than low, you can save DC power consumption through the final resistance. For GTL +, set the appropriate default status of the 50Ω end-to-end resistor to 1.5 V, saving each I/O power consumption by 30 mA.

Data enabling

When the data on the bus is related to registers, the chip selection or clock enabling logic is often used to control the register enabling. Further, enable the logic as early as possible to prevent unnecessary conversion between the data bus and the clock enable register combination logic, as shown in 1. The red waveform indicates the original design; the green waveform indicates the modified design.

 

Another option is to enable data on a circuit board rather than on a chip ". To minimize the CPU clock cycle. This concept is to use CPLD to detach a simple task from a processor so that it remains in standby mode for a longer time.

Let's look at a state machine that frequently performs state conversion between Status 7 and status 8. If you select binary encoding for the state machine, it means that four States need to be changed for each state transition between 7 and 8, as shown in table 1. If the state machine uses the Gray code instead of the binary code, the number of logical conversions required for the transition between the two states will be reduced to only one. In addition, if Status 7 and 8 are encoded as 0010 and 0011 respectively, the same effect can be achieved.

Clock management

The clock is the culprit among all the signals designed to absorb power consumption. Although a clock may run at 100 MHz, the signal derived from the clock usually runs at a smaller part of the main clock frequency (usually 12% ~ 15% ). In addition, the clock fan-out is generally relatively high-these two factors show that the clock should be carefully studied to reduce power consumption.

If a part of the design can be inactive, you can consider using a BUFG-MUX to prevent the Clock Tree from being flipped, rather than using the clock enabling. The clock enables unnecessary turning of the block registers, but the clock tree still throws and consumes power. However, there is no better way to use the clock.

Isolate the clock to use a minimum number of signal areas. The unused Clock Tree signal area does not flip, reducing the load on the clock network. Careful layout can be achieved without affecting the actual design.

The same concept can also be used for FPGA. Although FPGA does not necessarily have the standby mode, using a CPLD to intercept bus data and selectively feed the data to FPGA can also save unnecessary input conversion.

The coolrunner-ii cpld contains a feature called "Data Control" that prevents logical conversions on pins from reaching the internal logic of the CPLD. This data control enables on-chip logic or pin control.

State Machine Design

Lists the state machines based on the predicted next state condition, and selects the State values with fewer transitions between normal states. In this way, you can minimize the number (frequency) of state machine network conversions ). Determining Normal conversion and selecting appropriate State values is a simple method to reduce power consumption and minimize the impact on design. The simpler the encoding format (a valid encoding or Gray code), the less the decoding logic used.

Power Consumption Estimation tools

Xilinx provides two forms of Power Consumption Estimation tools: a pre-design tool called Web power tools and a post-design tool called xpower. Web power tools uses http://www.xilinx.com/cn/power to estimate the power consumption of logical utilization rate. With it, you can evaluate your power consumption by estimation of the design utilization, without the need for actual design documents.
Xpower is a post-design tool used to analyze the actual utilization of devices and provide actual power consumption data based on the Post-fit simulation data (VCD file format. With xpower, you can analyze the impact of design changes on total power consumption without getting in touch with the chip.

Web-based power consumption tools

Web-based power consumption estimation is the fastest and most convenient way to obtain the power consumption of devices in the early stages of the design process. These tools release new versions every quarter. Therefore, the information is always up-to-date and requires no installation or download. You only need to have Internet connections and web browsers. You can specify design parameters and save and load design settings to avoid the trouble of re-inputting design parameters through interaction. You only need to estimate the design behavior and select the target device.

Xpower: Integrated Design-Specific Power Consumption Analysis

Xpower is a free component of all Xilinx ISE design tools. You can use it to estimate your design-based power consumption requirements in more detail. Xpower is designed based on ing, layout, and cabling to estimate device power consumption.

For mature FPGA and CPLD, the average design batch error (suite error) calculated by xpower is less than 10%. It combines device data with your design documents and provides a high-precision report on device Power Consumption Estimation Based on your specific design information.

Xpower is directly integrated into ISE software and provides hierarchical and detailed Power Consumption display, detailed summary report, and power consumption wizard, which can be easily used by new users. Xpower can accept simulation design activity data and run in GUI and batch modes.

Xpower will consider each network and logical element in the design. The Ise design file provides accurate resource usage, xpower cross-reference wiring information, and characteristic capacitor data. Therefore, physical resources are characterized by capacitors. The design characteristics will continue for new devices to provide the most accurate results. Xpower uses the network flip rate and output load. The xpower computing power consumption and junction temperature can also display the power consumption data of a single network.

 

Conclusion

The ever-increasing demand for cheaper and simpler thermal management and power supplies that match the ever-increasing power consumption requirements of cutting-edge FPGAs has elevated the concept of low-power design to a new level. Xilinx's latest Virtex-4 FPGA device provides a 90 nm High performance technology, but avoids the expected increase in static power consumption. Using the Xilinx Power Consumption Estimation tool and following the Low Power Design considerations will make it easier to meet your power consumption goals than ever before.