Designing LCD to VGA with FPGA

This thing is actually done in the last winter, and it seems to have been industrialized, at that time was for a friend to do, this friend to sell to the industrialized people, like the story of a cliché, this friend got the money, but not as the project began to say that related to me. Think of the scenes of eating and drinking together many years ago, and sigh to erase those memories, can only forget. Now write this design in Boven Boven, on the one hand can recall memories of the design ideas at the time, but also hope that other design FPGA brothers and sisters to provide a little reference.

The PPT document that was written at that time can be downloaded at the following address:

Http://blogimg.chinaunix.net/blog/upfile2/101222213657.pdf

This board is actually on the s3c2410 board of the Rotten Street add a piece of FPGA Ep2c5,sdram and ADV7123. Since 2410 has an LCD controller, in the LCD interface to add a video DAC, the ADV7123 on the board can output VGA signal, you can connect the monitor. However, when the output resolution is too high, such as 1024x768 or even higher, the LCD interface requires too much bandwidth, which will affect the speed of the application above 2410.

Therefore, this design is designed to let 2410 output high-resolution low frame rate signals, such as [email protected], through the FPGA to the output of the image stored in its controlled SDRAM, The image generation part of the FPGA then reads the data and outputs it to ADV7123 at the speed of [email protected] .

This design for ECG monitoring such equipment is sufficient, because the ECG update less than 20HZ, in fact, it is suitable for all the requirements of the refresh rate is not high but to be connected to the VGA display.

The framework of the system is probably the above, the LCD receiver from the 2410LCD interface to receive data, in fact, after the detection of Hsync,vsync,vden through CLK will be data acquisition, and then stored in the FIFO, This part of the logic needs to be designed according to the 2410 LCD timing. Using FIFO has two uses, on the one hand is matching the speed of reading and writing, on the one hand is the conversion data width, because only with 2410 LCD output data in 8bit data, namely RGB332, and SDRAM and RW Control module are operating according to 16bit, Therefore, a 8bit input 16bit output FIFO can be converted.

The RW control module, as the name implies, is mainly for the SDRAM read and write controls, when received Dcfifo2 almost full when read Dcfifo2 write it to SRAM, when received dcfifo1 almost empty, Reading data from the SDRAM writes it to DCFIFO1 for the VGA module to convert. The Dcfifo1 is a FIFO with a 16bit input 8bit output, which has the opposite function and Dcfifo2.

The PLL, FIFO module is used in Altera quartus in the off-the-shelf module, SDRAM is also Altera's Open source module, Is Ref-sdr-sdram-verilog.zip, in Google search has a large pile, as long as the definition of the bus width where the change is almost ready to use, and other about the refresh time, such as SDRAM initialization parameters are in the RW When the control module starts, the command is issued, and the SDRAM control module is transmitted to the SDRAM chip.

The VGA generation module reads the image data from the DCFIFO1 and generates the corresponding signal control video DAC. The main thing is to understand the probability of the front shoulder, the back shoulder, in fact, each row (or a frame) behind and in front of the gap time. The output clock frequency is as consistent as possible to the standard specification.

Just like all development, design is only a small part of it, and the biggest part is debugging. Altera Signaltrap is equivalent to a free logic analyzer, although its storage depth is related to the memory size inside the chip, but it is quite convenient. How to use Application Note that can refer to Altera.

Resources

http://item.taobao.com/item.htm?spm=a1z10.5-c.w4002-2613737244.20.P9tQJG&id=43634840829

Designing LCD to VGA with FPGA