Detailed description and selection of FPGA chip configuration methods

Broadly speaking, FPGA configuration includes programming the FPGA device using the download cable, programming the external EEPROM and flash, programming the FPGA device using MPU, and programming the device using the external EEPROM and flash.

 

FPGA Devices are configured in three categories: Active configuration, passive configuration, and JTAG configuration.

 

Active configuration: the configuration process is guided by FPGA Devices.

Passive configuration: the configuration process is controlled by the computer or controller. After the device is powered on, the Controller or master sends the data stored in the external memory to the FPGA device. After the configuration is complete, the device I/O and registers are initialized. After Initialization is complete, enter user mode and start to work normally.

 

Once the designer selects the configuration method of the FPGA system, the msel pin on the device needs to be set as a fixed value to indicate the current configuration method.

 

Common configuration methods include:

1. Passive serial configuration: passive serial configuration
2. As configuration (active serial configuration): active serial configuration
3. PPS configuration (passive parallel synchronous configuration): passive parallel synchronization Configuration
4. Fast passive parallel configuration: Fast passive parallel Configuration
5. Passive parallel asynchronous configuration: passive parallel asynchronous Configuration
6. PSA configuration (passive Serial Asynchronous configuration): passive Serial Asynchronous Configuration
7. JTAG configuration (joint test action group configuration)