Detailed description of arm 44binit. s file

Detailed description of arm 44binit. s file

; **************************************** ***************
; * Name: 44binit. S *
; * Version: 10. jan.2003 *
; * Description :*
; * C start up codes *
; * Configure memory, initialize ISR, stacks *
; * Initialize C-variables *
; * Fill zeros into zero-initialized C-variables *
; **************************************** * ************** Get option. s; equivalent to # include "option in C. s"
Get memcfg. s; interrupt control
Declare some symbolic constants, which correspond to the address of the corresponding register
Intpnd equ 0x01e00004; indicates each bit in the interrupt request Status Register. For more information about which interrupt request is represented, see 44b0 spec.
Intmod equ 0x01e00008; the interrupt mode register has two kinds of interrupt mode. The corresponding bits are 1, indicating that FIP Mode 0 represents Riq mode.
Intmsk equ 0x01e0000c; Determine which interrupt source is blocked and the blocked interrupt source will not be served
I _ispr equ 0x01e00020; interrupt service suspension register
I _cmst equ 0x01e0001c; current Master Register IRQ priority; watchdog timer
Wtcon equ 0x01d30000; watchdog timer control register; clock Controller
Pllcon equ 0x01d80000; PLL control register
Clkcon equ 0x01d80004; clock control register
Locktime equ 0x01d8000c; lock time count value register; Memory Controller
Refresh equ 0x01c80024; DRAM/SDRAM refresh control register
The following is a constant definition of the value corresponding to the ARM processor mode register. The ARM processor has a CPSR Program Status Register. Its last five digits determine the current processor mode.
; Pre-defined Constants
Usermode equ 0x10; User Mode
Fiqmode equ 0x11; Fiq Mode
Irqmode equ 0x12; IRQ Mode
Svcmode equ 0x13; Management Mode
Abortmode equ 0x17; abort Mode
Undefmode equ 0x1b; undefined
Modemask equ 0x1f; System Mode
Noint equ 0xc0; check if tasm.exe is used.
The ARM processor has two working states: 1.arm: 32-bit. In this working state, the arm command executes the word aligning. 2. Thumb: 16-bit. In this working state, the half-word aligning thumb command is executed.
Because the processor is divided into 16-bit 32-bit working state, the compiler of the program is also divided into 16-bit and 32-bit compilation methods, so the following program is used to determine the compiler compilation mode based on the working state of the processor.
Code16 pseudo commands indicate 16-bit thumb commands after the compilation Compiler
Code32 pseudoinstruction indicates the 32-bit arm instruction after the Assembly Compiler
This section describes the operating status of the processor and the software compilation formula (16-bit compilation environment is compiled using tasm.exe)
Gbll thumbcode; set a global logical variable
[{Config} = 16; If Config = 16 this indicates that you are currently in the leading 16-bit compiling mode.
Thumbcode SETl {true}; Set thumbcode to true
Code32; transfer to 32-bit compiling Mode
|; Else
Thumbcode SETl {false}; Set thumbcode to false
] [Thumbcode; If thumbcode = true
Code32; for start-up code for thumb mode; transfer to 32-bit compilation Mode
]
Note: The following program is a macro definition. Many people do not understand this program. I emphasize that this is a macro definition. Therefore, you must note that the following handlerxxx handler handlexxx will be expanded in the following program.
This program is used to load the first address of the interrupted service program to the PC. Someone calls it "loading the program ".
The initialization program defines a data zone (at the end of the file) with 34 characters to store the first address of the corresponding interrupted service program. Each word space has a label named after handle.
In vector interrupt mode, use "loader" to execute the interrupt service program.
Here we must talk about the concepts of the vector interrupt mode and the non-vector interrupt mode.
In vector interrupt mode, when the CPU reads the IRQ interrupt command at 0x18, the system automatically reads the command at the specified address of the interrupt source to replace the command at 0x18, jump directly to the corresponding address through the jump command system
The function saves the interrupt processing time and increases the interrupt processing speed. For example, if the vector address of the ADC interrupt is 0xc0, run the following code at 0xc0: ldr pc, = handleradc the system will
; Automatically jump to the handleradc Function
Non-vector interrupt mode is a traditional interrupt processing method, the system redirects the corresponding flag position in the interrupt pending register to the unified interrupt at 0x18.
In the function, the function reads the corresponding flag in the interrupt pending register to determine the interrupt source and jumps to the processing code of the corresponding interrupt source based on the priority relationship.
Macro
$ Handlerlabel handler $ handlelabel $ handlerlabel
Sub sp, SP, #4; Decrement Sp (to store jump address)
Stmfd SP !, {R0}; ads only supports FD (full decline) type stacks; R0 registers to be used into the stack
LDR r0, = $ handlelabel; load the address of handlexxx to R0
LDR r0, [R0]; load the contents (service routine start address) of handlexxx
STR r0, [Sp, #4]; store the contents (ISR) of handlexxx to stack; Add the first address of the corresponding interrupt function to the stack
Ldmfd SP !, {R0, PC}; pop the work register and PC (jump to ISR)
; Puts the first address of the interrupt function out of the stack and into the PC, the system will jump to the corresponding Interrupt Processing Function
Mend
An arm consists of three segments: RO, RW, and Zi. Ro is the code segment, and RW is the initialized global variable, zi is an uninitialized global variable (the GNU tool corresponds to the concept of text, Data, BSS) bootloader
; Bootloader needs to copy the RW segment to Ram and clear the Zi segment. The compiler uses the following segment to record the start and end addresses of each segment.
; | Image $ Ro $ base |; start address of the RO segment
; | Image $ Ro $ limit |; Add 1 to the end address of the RO segment
; | Image $ RW $ base |; start address of the RW segment
; | Image $ RW $ limit |; Add 1 to the RW segment end address
; | Image $ Zi $ base |; start address of the Zi segment
; | Image $ Zi $ limit |; Add 1 to the end address of the Zi segment
The value of these labels is determined by the compiler settings, such as the ro-base and RW-base settings in the compilation software, for example, ro-base = 0xc000000 RW-base = 0xc5f0000 import | image $ Ro $ limit |; end of ROM code (= start of Rom data)
Import | image $ RW $ base |; base of Ram to initialise
Import | image $ Zi $ base |; base and limit of area
Import | image $ Zi $ limit |; to zero initialise import main; the main entry of Mon Program
; Below is the code snippet
Area init, code, readonly; declare a code segment named init and the attribute is read-only. The exception interrupt vector table (each table item occupies 4 bytes) the following figure shows the interrupt vector table. Once the system is running, the interrupt occurs. Even if the operating system is transplanted, for example, the Linux processor has handed over the control to the operating system, the processor will jump from 0x0.
An interrupt table entry in the interrupt vector table (based on the interrupt type ).
For details about the interrupt vector layout, refer to the 49th position vector address 0x0 + 4 * (49-1) = 0x000000c0 In the table corresponding to the position vector in the spec. For example, the ADC interrupt vector is 0x000000c0.
Entry
; After power-on and reset, the program starts to execute from 0x0. After the hardware is powered on and reset, the program starts to execute from here and jumps to the resethandler to execute 1. From the code, the init segment is to write 0x00 original interrupt vector of the address, therefore, compile the 44binit file. O and init are filled in the corresponding items on the linker-layout page of ADS (this way, the compiler will compile the code to the 0x0 address. 1. About 44b0 Interrupt System
There are two interrupt transfer tables in the 44b0 interrupt system. After the dual transfer, the table jumps to the interrupt processing program. The first interrupt vector table is determined by the hardware. Its region is Rom (flash). The address space starts from 0x00. 0x00-0x1c is the exception vector entry address, and 0x20-0xc0 is the interrupt vector entry address. Another interrupt vector table is in Ram and can be changed randomly. Its position is determined after the program is connected. B resethandler; For debug
B handlerundef; handlerundef
B handlerswi; SWI interrupt handler
B handlerpabort; handlerpabort
B handlerdabort; handlerdabort
B.; handlerreserved
B handlerirq
B handlerfiq
; *** Important note ***
; If the H/W vectored interrutp mode is enabled, the above two instructions shoshould
; Be changed like below, to work-around with H/W bug of fig controller.
; B handlerirq-> subs PC, LR, #4
; B handlerirq-> subs PC, LR, #4 2. How to jump from the first interrupt vector table to the second interrupt vector table
Because Ram is placed at the high end of the address space (32 m away from the interrupt vector), write ldr pc in the corresponding position of the first interrupt vector table. # interrupt_service such as: ldr pc, = handlereint4567. In fact, the exception vector is the interrupt vector. In fact, the kernel of ARM7 only has eight (one retained) exception vectors. For many interrupt sources, the kernel of ARM7 obtains the starting address of Isr by querying the bit of the interrupt Status Register in IRQ and frq software.
44b0 adds more interrupt vector meters (0x20 to 0xc0) to overcome the interruption delay caused by this method, in the interrupt control register, you must set the mode of each interrupt source to IRQ and use vector interrupt.
Vector_branch
Ldr pc, = handlereint0; mga h/W interrupt vector table
Ldr pc, = handlereint1;
Ldr pc, = handlereint2;
Ldr pc, = handlereint3;
Ldr pc, = handlereint4567;
Ldr pc, = handlertick; MGA
B.
B.
Ldr pc, = handlerzdma0; MGB
Ldr pc, = handlerzdma1;
Ldr pc, = handlerbdma0;
Ldr pc, = handlerbdma1;
Ldr pc, = handlerwdt;
Ldr pc, = handleruerr01; MGB
B.
B.
Ldr pc, = handlertimer0; MGC
Ldr pc, = handlertimer1;
Ldr pc, = handlertimer2;
Ldr pc, = handlertimer3;
Ldr pc, = handlertimer4;
Ldr pc, = handlertimer5; MGC
B.
B.
Ldr pc, = handlerurxd0; MGD
Ldr pc, = handlerurxd1;
Ldr pc, = handleriic;
Ldr pc, = handlersio;
Ldr pc, = handlerutxd0;
Ldr pc, = handlerutxd1; MGD
B.
B.
Ldr pc, = handlerrtc; mgka
B .;
B .;
B .;
B .;
B. mgka
B.
B.
Ldr pc, = handleradc; mgkb
B .;
B .;
B .;
B .;
B.; mgkb
B.
B.
Ldr pc, = enterpwdn; 0xe0 = enterpwdn2. Through this code, an interrupt vector table is created at the starting address of 0x00 in the 44b0 Rom, in addition, the order of the table fully complies with the definition requirements of the interrupt vector address in the 44b0 Data Manual. Ltorg; ltorg is used to declare a data buffer pool.
The following is the macro to jump to the specific interrupt handler function. The macro definition of $ handlerlabel above is expanded to jump to the corresponding interrupt handler function (for vector interrupt)
Handlerfiq handler handlefiq
Handlerirq handler handleirq
Handlerundef handler handleundef
Handlerswi handler handleswi
Handlerdabort handler handledabort
Handlerpabort handler handlepabort handleradc handler handleadc
Handlerrtc handler handlertc
Handlerutxd1 handler handleutxd1
Handlerutxd0 handler handleutxd0
Handlersio handler handlesio
Handleriic handler handleiic
Handlerurxd1 handler handleurxd1
Handlerurxd0 handler handleurxd0
Handlertimer5 handler handletimer5
Handlertimer4 handler handletimer4
Handlertimer3 handler handletimer3
Handlertimer2 handler handletimer2
Handlertimer1 handler handletimer1
Handlertimer0 handler handletimer0
Handleruerr01 handler handil-err01
Handlerwdt handler handlewdt
Handlerbdma1 handler handlebdma1
Handlerbdma0 handler handlebdma0
Handlerzdma1 handler handlezdma1
Handlerzdma0 handler handlezdma0
Handlertick handler handletick
Handlereint4567 handler handleeint4567
Handlereint3 handler handleeint3
Handlereint2 handler handleeint2
Handlereint1 handler handleeint1
Handlereint0 handler handleeint0; one of the following two routines can be used for non-Vectored Interrupt.
The following program is used to handle non-vector interruptions. In I _ispr, if you set 1 to 1, this interrupt is waiting for response (only one position is allowed at a time ), starts from the highest priority interrupt bit and detects waiting for the service.
When the service is interrupted, the PC is set to the first address of the function to be interrupted.
Isrirq; using I _ispr register.
Sub sp, SP, #4; reserved for PC, left blank for PC
Stmfd SP !, {R8-r9}; put R8, R9 into the stack first; important caution
; If I _ispc isn't used properly, I _ispr can be 0 in this routine. LDR R9, = I _ispr; read the value in I _ispr
LDR R9, [R9]
MoV R8, #0x0
0
Movs R9, R9, LSR #1; logically shift right to get the number of the interrupt source
BCS % F1
Add R8, R8, #4
B % B0; jump back to the place where the label is 0 1
LDR R9, = handleadc
Add R9, R9, R8; to get the offset address
LDR R9, [R9]; obtain the corresponding IRQ program address.
STR R9, [Sp, #8]; Use the IP address of the IRQ program as the PC value into the stack
Ldmfd SP !, {R8-r9, PC}; out of stack, to the new interrupt program; **************************************** ************
; * Start *
; **************************************** ************
After the wrench is powered on and reset, the program starts to execute the B resethandler program from 0x0 and starts to jump to here for execution.
After the Board is powered on and reset, perform several steps. Here, add 1, 2, 3... to the comment to indicate the sequence of execution.
1. Disable the watchdog to block all interruptions.
Resethandler
LDR r0, = wtcon; watch dog disable
LDR R1, = 0x0
STR R1, [R0] LDR r0, = intmsk
LDR R1, = 0x07ffffff; all interrupt disable
STR R1, [R0]
2. Set the PLL according to the working frequency
Here we will introduce the calculation formula
; Fpllo = (M * fin)/(p * 2 ^ s)
; M = mdiv + 8, P = pdiv + 2, s = sdiv
; Fpllo must be greater than 20 MHz and smaller than 66 MHz
; Fpllo * 2 ^ s must be less than 170 MHz
; M_div p_div s_div in pllcon settings below is taken from option. h
; # Elif (mclk = 40000000)
; # Define pll_m (0x48)
; # Define pll_p (0x3)
; # Define pll_s (0x2)
So M = mdiv + 8 = 80, P = pdiv + 2 = 5, S = sdiv = 2
The hardware uses a 10 MHz crystal oscillator, that is, fin = 10 MHz.
; Fpllo = 80*10/5*2 ^ 2 = 40 MHz; **************************************** ************
; * Set clock control registers *
; **************************************** ************
LDR r0, = locktime
LDR R1, = 800; Count = t_lock * fin (t_lock = 200us, fin = 4 MHz) = 800
STR R1, [R0] [pllonstart
LDR r0, = pllcon; temporary setting of PLL
LDR R1, = (m_div <12) + (p_div <4) + s_div); fin = 10 MHz, fout = 40 MHz
STR R1, [R0]
] LDR r0, = clkcon
LDR R1, = 0x7ff8; All unit block CLK enable
STR R1, [R0]
3. Set the program for storing the relevant registers
This is the Program for configuring the connection and Working Sequence of the SDRAM, Flash ROM memory, and the program defined by the chip selection.
; Smrdata map is defined in the following program
For the values involved in smrdata, see the memcfg. s program.
For more information about the registers, see the spec; **************************************** ************
; * Set memory control registers *
; **************************************** ************
LDR r0, = smrdata
Ldmia r0, {R1-R13}
LDR r0, = 0x01c80000; bwscon address
Stmia r0, {R1-R13 }; **************************************** ************
; * Initialize stacks *
; **************************************** ************
LDR sp, = svcstack; why?
BL initstacks
5. Set the default Interrupt Processing Function
; **************************************** ************
; * Setup IRQ handler *
; **************************************** ************
LDR r0, = handleirq; this routine is needed
LDR R1, = isrirq; If there isn 't'subs PC, LR, # 4' at 0x18, 0x1c
STR R1, [R0]
6. copy the data segment to Ram and clear the zero-initialization data segment and jump into the main function of C language. Execute this step to complete the bootloader preliminary guide.
; **************************************** ****************
; * Copy and paste RW data/Zero initialized data *
; **************************************** ****************
LDR r0, = | image $ Ro $ limit |; get pointer to Rom data
LDR R1, = | image $ RW $ base |; and ram copy
LDR R3, = | image $ Zi $ base |
; Zero init base => top of initialised data program first copies the initial RW data in ROM | image $ Ro $ limt | to ram | image $ RW $ Base | start address, when the target address of the ram side reaches | image $ Zi $ base |, it indicates the end of the RW area and the start of the Zi area. Then, the Zi area is cleared, until the end address is reached | image $ Zi $ limit |.
CMP r0, R1; check that they are different
Beq % F1
0
CMP R1, R3; copy init data
Ldrcc R2, [R0], #4; --> ldrcc R2, [R0] + Add r0, R0, #4
Strcc R2, [R1], #4; --> strcc R2, [R1] + Add R1, R1, #4
BCC % B0
1
LDR R1, = | image $ Zi $ limit |; top of zero init segment
MoV R2, #0
2
CMP R3, R1; zero init
Strcc R2, [R3], #4
BCC % B2 [: lnot: thumbcode
BL main; don't use main () Because ......; jump into the main function
B.
] [Thumbcode; for start-up code for thumb Mode
Orr lr, PC, #1
BX lR
Code16
BL main; don't use main () Because ......; jump into the main function
B.
Code32
]
4. initialize the stack pointer in each mode
; **************************************** ************
; * The function for initializing stack *
; **************************************** ************
Initstacks
; Don't use dram, such as sans FD, ldmfd ......
; Svcstack is initialized before
; Under toolkit ver 2.50, 'msr CPSR, r1' can be used instead of 'msr cpsr_cxsf, r1' Mrs r0, CPSR
Bic r0, R0, # modemask
ORR R1, R0, # undefmode | noint
MSR cpsr_cxsf, R1; undefmode
LDR sp, = undefstack Orr R1, R0, # abortmode | noint
MSR cpsr_cxsf, R1; abortmode
LDR sp, = abortstack Orr R1, R0, # irqmode | noint
MSR cpsr_cxsf, R1; irqmode
LDR sp, = irqstack Orr R1, R0, # fiqmode | noint
MSR cpsr_cxsf, R1; fiqmode
LDR sp, = fiqstack Bic r0, R0, # modemask | noint
ORR R1, R0, # svcmode
MSR cpsr_cxsf, R1; svcmode
LDR sp, = svcstack; user mode is not initialized.
MoV PC, LR; the LR register may be not valid for the mode changes.
The following is the definition of related registers in pwdn mode.
; **************************************** ************
; * The function for entering power down mode *
; **************************************** ************
; Void enterpwdn (INT clkcon );
Enterpwdn
MoV R2, R0; R0 = clkcon
LDR r0, = Refresh
LDR R3, [R0]
MoV R1, r3
ORR R1, R1, #0x400000; self-Refresh enable
STR R1, [R0] NOP; wait until self-refresh is issued. may not be needed.
NOP; if the other bus master holds the bus ,...
NOP; MoV r0, R0
NOP
NOP
NOP
NOP; enter powerdn Mode
LDR r0, = clkcon
STR R2, [R0]; wait until enter sl_idle, stop mode and until wake-up
MoV r0, # 0xff
0 subs r0, R0, #1
BNE % B0; exit from DRAM/SDRAM self refresh mode.
LDR r0, = Refresh
STR R3, [R0] mov PC, LR ltorg
; This is the previously mentioned Data Map for storage register Initialization
Smrdata data
; **************************************** *************************
; * Memory configuration has to be optimized for best performance *
; * The following parameter is not optimized .*
; **************************************** *************************; * ** Memory access cycle parameter strategy ***
(1) Even FP-DRAM, Edo setting has more late fetch point by half-clock
; 2) the memory settings, here, are made the safe parameters even at 66 MHz.
3) FP-DRAM parameters: trcd = 3 for TRAC, TCAS = 2 for pad delay, TCP = 2 for bus load.
; 4) DRAM refresh rate is for 40 MHz. DCD 0x11110090; bank0 = om [1:0], bank1 ~ Bank7 = 16bit, bank2 = 8bit;
DCD (b0_tacs <13) + (b0_tcos <11) + (b0_tacc <8) + (b0_tcoh <6) + (b0_tah <4) + (b0_tacp <2) + (b0_pmc); gcs0
DCD (b1_tacs <13) + (b1_tcos <11) + (b1_tacc <8) + (b1_tcoh <6) + (b1_tah <4) + (bw.tacp <2) + (bw.pmc); gcs1
DCD (b2_tacs <13) + (b2_tcos <11) + (b2_tacc <8) + (b2_tcoh <6) + (b2_tah <4) + (b2_tacp <2) + (b2_pmc); gcs2
DCD (b3_tacs <13) + (b3_tcos <11) + (b3_tacc <8) + (b3_tcoh <6) + (b3_tah <4) + (b3_tacp <2) + (b3_pmc); gcs3
DCD (b4_tacs <13) + (b4_tcos <11) + (b4_tacc <8) + (b4_tcoh <6) + (b4_tah <4) + (b4_tacp <2) + (b4_pmc); gcs4
DCD (b5_tacs <13) + (b5_tcos <11) + (b5_tacc <8) + (b5_tcoh <6) + (b5_tah <4) + (b5_tacp <2) + (b5_pmc); gcs5
DCD (b6_mt <15) + (b6_trcd <2) + (b6_scan); gcs6
DCD (b7_mt <15) + (b7_trcd <2) + (b7_scan); gcs7
DCD (refen <23) + (trefmd <22) + (Trp <20) + (TRC <18) + (TCHR <16) + refcnt ); refresh rfen = 1, trefmd = 0, TRP = 3clk, TRC = 5clk, TCHR = 3clk, Count = 1019
DCD 0x16; sclk power mode, banksize 32 M/32 m
DCD 0x20; mrsr6 Cl = 2clk
DCD 0x20; mrsr7 align; The following is the definition of the ram region map.
Area ramdata, Data, readwrite
Here we define the stack zone where the processor works in each mode map in Ram
^ (_ ISR_STARTADDRESS-0x500); map; field userstack #256; C1 (C7) ffa00
Svcstack #256; C1 (C7) ffb00
Undefstack #256; C1 (C7) ffc00
Abortstack #256; C1 (C7) ffd00
Irqstack #256; C1 (C7) ffe00
Fiqstack #0; C1 (C7) fff00; the interrupt exception vector is built in the SDRAM
^ _ Isr_startaddress
Handlereset #4
Handleundef #4
Handleswi #4
Handequalabort #4
Handledabort #4
Handlereserved #4
Handleirq #4
Handlefiq #4; don't use the label 'intvectortable ',
; Because armasm.exe cann't recognize this label correctly.
; The value is different with an address you think it may be.
; Intvectortable
Handleadc #4
Handlertc #4
Handleutxd1 #4
Handleutxd0 #4
Handlesio #4
Handleiic #4
Handleurxd1 #4
Handleurxd0 #4
Handletimer5 #4
Handletimer4 #4
Handletimer3 #4
Handletimer2 #4
Handletimer1 #4
Handletimer0 #4
Handleuerr01 #4
Handlewdt #4
Handlebdma1 #4
Handlebdma0 #4
Handlezdma1 #4
Handlezdma0 #4
Handletick #4
Handleeint4567 #4
Handleeint3 #4
Handleeint2 #4
Handleeint1 #4
Handleeint0 #4; 0xc1 (C7) fff84 end
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