Detailed explanation and analysis of lspci

Source: Internet
Author: User

1. Introduction to PCI
PCI is a peripheral bus specification. Let's first look at what bus is: Bus is a path or channel for transmitting signals. Typically, a bus is an electrical connection that is connected to one or more conductors. All devices connected to the bus can receive all the transmission content at the same time. The bus consists of electrical interfaces and programming interfaces. This article discusses device drivers in Linux, so focus on programming interfaces.
PCI is short for Peripheral Component Interconnect (peripheral device interconnection). It is an external bus widely used on desktops and larger computers. The PCI architecture is designed as an ISA standard alternative with three main objectives: to achieve better performance in data transmission between computers and peripherals; to be as platform independent as possible; simplify adding and deleting peripherals to and from the system.

Ii. PCI addressing
From now on, I want to explain the problem through some practical examples as much as possible, and reduce the descriptive descriptions of theoretical problems, it can be found elsewhere.
Let's take a look at an example. My computer is equipped with 1 gb ram. The physical memory address space after 1 GB is the ing of external device Io on the system memory address space. The/proc/iomem description describes the ing of all device I/O in the system on the memory address space. Let's take a look at how the first device starting from 1G describes in/proc/iomem:
40000000-400003ff: 0000: 00: 1f. 1
This is a PCI device. 40000000-400003ff is the memory address space mapped to it, occupying the location of 1024 bytes of the memory address space, while 0000: 00: 1f. 1 is the IP address of a PCI peripheral. It is separated by a colon and a comma into four parts. The first 16-bit represents the domain, and the second 8-bit represents a bus number, the third and fifth digits indicate a device number, and the last three digits indicate the function number.

The PCI specification allows a single system to have up to 256 buses, so the bus number is 8 bits. However, this is not enough for large systems. Therefore, the concept of a domain is introduced. Each PCI domain can have up to 256 buses, and each bus can support 32 devices, therefore, the device number is five bits, and each device can have a maximum of eight functions, so the function number is three bits. As a result, we can obtain that the IP address of the above PCI device is the No. 1 function of the No. 31 device on the Bus No. 0 in the 0 domain.

So what is the above PCI device? The following is the output of the lspci command on my computer:
. 0 host bridge: Intel Corporation 82845 845 (Brookdale) chipset host bridge (Rev 04)
. 0 PCI Bridge: Intel Corporation 82845 845 (Brookdale) chipset AGP bridge (Rev 04)
00: 1d. 0 USB controller: Intel Corporation 82801ca/cam usb (hub #1) (Rev 02)
00: 1d. 1 USB controller: Intel Corporation 82801ca/cam usb (hub #2) (Rev 02)
00: 1E. 0 PCI Bridge: Intel Corporation 82801 mobile PCI bridge (Rev 42)
00: 1f. 0 ISA Bridge: Intel Corporation 82801cam ISA bridge (LPC) (Rev 02)
00: 1f. 1 ide interface: Intel Corporation 82801cam ide u100 (Rev 02)
00: 1f. 3 SMBus: Intel Corporation 82801ca/CAM SMBus controller (Rev 02)
00: 1f. 5 multimedia audio Controller: Intel Corporation 82801ca/CAM ac'97 Audio Controller (Rev 02)
00: 1f. 6 modem: Intel Corporation 82801ca/cam ac '97 modem controller (Rev 02)
. 0 VGA compatible Controller: NVIDIA Corporation nv17 [geforce4 420 go] (Rev A3)
. 0 FireWire (IEEE 1394): via Technologies, Inc. IEEE 1394 host controller (Rev 46)
. 0 Ethernet controller: RealTek semiconduco., Ltd. RTL-8139/8139c/8139c + (Rev 10)
. 0 carw.bridge: O2 micro, Inc. oz6933 carw.controller (Rev 01)
. 1 carw.bridge: O2 micro, Inc. oz6933 carw.controller (Rev 01)
Lspci does not indicate the domain, but for a PC, there is generally only one domain, that is, the 0 domain. Through this output, we can see that it is an IDE interface. From the above output, we can see that my computer has three PCI buses (0, 1, 2 ). In a single system, the insertion of multiple bus is completed through the bridge, which is a special PCI peripherals used to connect the bus. Therefore, the overall layout of the PCI system is structured in a tree. We can use the above lspci output to draw a tree structure of the PCI system on my computer:
. 0 (Main Bridge) --. 0 (PCI bridge) ----- (NVIDIA graphics card)
|
| --- 00: 1d (USB controller) -- 00: 1D: 0 (usb1 Controller)
|
| -- 00: 1D: 1 (usb2 Controller) |
|-00: 1E: 0 (PCI bridge) -- 0: 00. 0 (ieee1394)
|
|-. 0 (8139 Nic)
|
|-(Carton Bridge)-. 0 (bridge 1)
|
| --. 1 (Bridge 2)
|
|-00: 1f (multi-function board)-00: 1f: 0 (ISA Bridge)
|
| -- 00: 1f: 1 (IDE Interface)
|
| -- 00: 1f: 3 (SMBus)
|
| -- 00: 1f: 5 (multimedia sound Controller)
|
| -- 00: 1f: 6 (modem)
It can be concluded that my computer has eight PCI devices, four on Bus No. 0 (Main Bridge) and one on bus no. 1, there are 3 connected to Bus 2. 00: 1f is a multi-function board with five functions connected.
Each PCI device has its mapped Memory Address Space and Its I/O Region, which is easier to understand than memory. In addition, the PCI device also has its configuration registers. With the configuration register, the PCI driver does not need to probe the token to be able to ask the device. The configuration register layout is standardized. The four bytes of the configuration space contain a unique feature ID. Therefore, the driver can identify its devices by querying the specific IDS of peripherals. Therefore, the main innovation of PCI interface standards above ISA lies in configuring the address space.
As mentioned above, the PCI driver does not need to probe the receiver to be able to ask the device, thanks to the configuration of the address space. During the system boot phase, the PCI hardware device remains inactive, but each PCI motherboard is equipped with a firmware that can process PCI. The firmware reads and writes the registers in the PCI Controller, provides a question about the address space configured for the device.
The first 64 bytes of the configured address space are standardized. It provides information such as the manufacturer ID, device number, and version, and uniquely identifies a PCI device. At the same time, it also provides up to six I/O address areas, each of which can be memory or I/O address. These I/o address areas are the only way for the driver to find the specific location of the device mapped to the memory and I/O space. With these two points, the PCI driver completes the function equivalent to probe the slave. For details about the configuration space of these 64 bytes, refer to "Linux driver 3" p306.
Next, let's take a look at the configuration space of the 8139too Nic device. In the 2.6 kernel system, you can see a folder named after the PCI device in the/sys/bus/PCI/Drivers/folder, it doesn't mean that these devices exist in your system. Go to the 8139too folder, which contains a folder named after its device address 0000: 02: 01.0. In this folder, you can find a lot of information related to the NIC device. Resource records its six I/O address regions. The content is as follows:
0x0000000000003400 0x00000000000034ff 0x0000000000000101
0x00000000e0000800 0x00000000e00008ff 0x0000000000000200
0x0000000000000000 0x0000000000000000 0x0000000000000000
0x0000000000000000 0x0000000000000000 0x0000000000000000
0x0000000000000000 0x0000000000000000 0x0000000000000000
0x0000000000000000 0x0000000000000000 0x0000000000000000
0x0000000000000000 0x0000000000000000 0x0000000000000000
The file shows that the 8139too device uses two I/O address areas. The first is the I/O port range mapped to it, and the second is the memory address space mapped to it. The two values can be verified in/proc/iomem and/proc/ioport.

-[]-+-00.0
+-02.0
+-1d. 0
+-1d. 1
+-1d. 2
+-1d. 7
+-1E. 0-[] -- +-02.0
|/-05.0
+-1f. 0
+-1f. 1
+-1f. 3
/-1f. 5
00:00. 0 host bridge: Intel Corporation 82845g/GL [Brookdale-G]/GE/pe dram controller/Host-hub interface (Rev 03)
00:02. 0 VGA compatible Controller: Intel Corporation 82845g/GL [Brookdale-G]/Ge chipset integrated graphics device (Rev 03)
00: 1d. 0 USB controller: Intel Corporation 82801db/DBL/DBM (ich4/ICH4-L/ICH4-M) USB uhci controller #1 (Rev 02)
00: 1d. 1 USB controller: Intel Corporation 82801db/DBL/DBM (ich4/ICH4-L/ICH4-M) USB uhci controller #2 (Rev 02)
00: 1d. 2 USB controller: Intel Corporation 82801db/DBL/DBM (ich4/ICH4-L/ICH4-M) USB uhci controller #3 (Rev 02)
00: 1d. 7 USB controller: Intel Corporation 82801db/DBM (ich4/ICH4-M) usb2 EHCI controller (Rev 02)
00: 1E. 0 PCI Bridge: Intel Corporation 82801 PCI bridge (Rev 82)
00: 1f. 0 ISA Bridge: Intel Corporation 82801db/DBL (ich4/ICH4-L) LPC interface bridge (Rev 02)

(LPC hub controller 1)
00: 1f. 1 ide interface: Intel Corporation 82801db (ich4) ide controller (Rev 02)
00: 1f. 3 SMBus: Intel Corporation 82801db/DBL/DBM (ich4/ICH4-L/ICH4-M) SMBus controller (Rev 02)
00: 1f. 5 multimedia audio Controller: Intel Corporation 82801db/DBL/DBM (ich4/ICH4-L/ICH4-M) ac'97 Audio Controller (Rev 02)
0:02. 0 Communication Controller: conexant HSF 56 K hsfi modem (Rev 01)
0:05. 0 Ethernet controller: RealTek semiconduco., Ltd. RTL-8139/8139c/8139c + (Rev 10)

Detailed explanation and analysis of lspci

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