Development History of CPU/RAM/IO bus in PC architecture

1. Starting from the ibm pc xt architecture...

In the initial PC design, CPU, ram, and I/O are connected by a bus, and all components must work in the synchronous mode, the CPU determines the frequency at which other devices operate. This will bring about a locked to each other effect, that is, everyone is limited to a universal clock frequency (clock frequency) that all devices can withstand, the overall performance of the system is not high.

2. The first splitting of the bus

In 1987, Compaq came up with a way to split the system bus from the I/O bus so that two different buses can work on different clock frequencies. The CPU and memory still work on their own public bus (the system bus), independent of all I/O devices, this can free high-speed CPU/Ram components from the limitations of low-speed I/O devices.

The bridge here is the predecessor of the south bridge chip we are talking about now, and here we can see that the bridge actually plays a role in downgrading (similar to the amd K8 CPU division mechanism ).

3. Appearance of CPU Multiplier

Starting from 80486, the CPU has developed rapidly and the frequency has risen sharply. The memory has become unable to keep up with the CPU development pace! Intel decided to introduce the concept of frequency doubling (clock Doubler) in 80486! The memory still works on the system bus and maintains the same operating frequency as the system bus, while the actual internal operating frequency of the CPU (that is, the CPU clock speed we often say) is:

CPU clock speed = External frequency (system bus frequency/system bus frequency) * Frequency Doubling (clock Doubler)
CPU clock speed = 33 MHz * 2 = 66 MHz

In the example of Intel P4 2.8c: 200 MHz * 14 = 2800 MHz = 2.8 GHz

4. emergence of beiqiao chip/frontend Bus

From the previous points, we can see that the trend of PC structure change is to isolate devices with slow speeds and devices with fast speeds by cutting the bus. After that, the North Bridge Chip was finally developed! The bus between the memory and the North Bridge is called the memory bus. This bus connects the CPU and the North Bridge into the front side bus (FSB), that is, the system bus )!

Thanks to Intel's QDR (quad data rate) technology, the CPU of Pentium 4 can transmit data four times per clock cycle, so when the FSB operates at MHz, the equivalent frequency of FSB is 200 MHz * 4 = 800 MHz!

Note: FSB 800 is the equivalent frequency of FSB, not the actual working frequency of FSB!