Differences between sccb bus and I2C bus (reprinted)

Source: Internet
Author: User

Reprinted at: user1/2524/archives/2008/49949 .html

Sccb Bus


Sccb is the simplified I2C protocol, the SiO2-L is the serial clock input line, and the SIO-O is the serial bidirectional data line, which is equivalent to the I2C Protocol respectively. The bus sequence of sccb is basically the same as that of I2C. Its response signal Ack is called the 9th-bit of a transmission unit, which is divided into don't care and Na. Don't care bit is generated by the slave machine; NA bit is generated by the host. Because sccb does not support multi-byte read/write, the NA bit must be high. In addition, sccb does not have the concept of repeated start. Therefore, in the sccb reading cycle, when the host sends an in-chip Register address, it must send a bus stop condition. Otherwise, the slave cannot generate the don't care response signal when sending the READ command.

Due to some minor differences between I2C and sccb, gpio is used to simulate the sccb bus. The pins connected by the SCL are always set as the output mode, while the pins connected by the SDA dynamically change the input/output modes of the pins by setting the iodir value during data transmission. The write cycle of sccb directly uses the write cycle timing of the I2C bus protocol, while the read cycle of the SC-CB adds a bus stop condition.

Sccb is the same protocol as I2C. Sio_c and sio_d are the clock lines and data lines of sccb bus respectively. Currently, sccb bus communication protocol only supports transmission speed of KB/s or kb/s, and supports two address formats: ① slave device address (ID address, 8bit ), it can be divided into read address and write address. The high 7-bit is used to select the chip, and The 0th-bit is the read/write control bit (R/W), which determines whether to perform read or write operations on the chip; ② The internal register unit address (sub _ address, 8 bit) is used to determine which register unit is operated internally. It usually supports continuous multi-byte sequential read/write operations on the address unit. The implementation of the sccb control bus function relies entirely on the levels of the sio_c and sio_d bus and their mutual cooperation. Start and Stop conditions for sccb bus Transmission

Process: Use a simple three-phase (phase) Data Writing method, that is, in the process of writing the register, the ov7649 ID address is sent first ), then, send the destination Register address (sub_address) of the write data, and finally send the data to be written (write data), as shown in figure 3. If data is written to a continuous register, after a register is written, ov7649 automatically adds 1 to the Register address,ProgramYou can continue writing down without entering the ID address again, so that the three-phase write data is changed to two-phase write data. Because the system only needs to configure a limited number of non-continuous registers, if you configure all the registers, it will waste a lot of time and resources. Therefore, we only need to write data to the registers that need to change the data. Three-phase data writing is used for each register to be changed.

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