Differences between single-chip I/O port push-pull output and open-drain output

Differences between single-chip I/O port push-pull output and open-drain output)

Push-pull output: outputs high and low levels and connects to digital devices;

Open-drain output: the output end is equivalent to the collector of the transistor. To obtain a high-level state, the output end must be able to pull up the resistor. It is suitable for current-type drive and has a strong ability to absorb the current (generally less than 20 mA ).

The push-pull structure generally refers to the two transistors being controlled by the two complementary signals, which always end when one transistor is turned on.

Let's talk about the structure of open collector output. As shown in structure 1 of open collector output, the transistor on the right has no collector, so it is called open collector (the transistor on the left is used for reverse conversion, so that when the input is "0, the output is also "0 "). For Figure 1, when the input on the left side is "0", the front transistor cutoff (that is, the gap between the collector C and the emission pole e is equivalent to disconnecting ), therefore, the 5 V power supply is added to the transistor on the right through a 1 K resistor, And the transistor on the right (that is, a switch is closed). When the input on the left side is "1", the front transistor is turned on, while the end of the transistor (equivalent to switching off ).

We simplified figure 1 to figure 2. The switch in Figure 2 is under software control. It is disconnected when "1" and closed when "0. Obviously, when the switch is closed, the output is directly grounded, so the output level is 0. When the switch is disconnected, the output end is suspended, that is, the high-impedance state. The level status is unknown. If a resistance load (even a light load) arrives at the ground, the output level will be pulled to a low level by the load, therefore, this circuit cannot output a high level.

See figure 3. In Figure 3, the 1 K resistance is the pull-up resistance. If the switch is closed, the current will flow from the 1 K resistor and switch, but the other three ports will be pulled up internally due to the switch). When we want to use the input function, you only need to set the output port to 1, which is equivalent to disconnecting the switch. For P0 port, it is a high-impedance state.

For open-circuit (OD) output, the output is very similar to that of Open-collector output. Replace the above transistor with a Fet. In this way, the collector becomes the drain pole, the OC becomes the OD, And the principle analysis is the same.

Another output structure is push-pull output. The structure of the push-pull output is to replace the above pull-up resistor with a switch. When high-power output is required, the switch above is enabled and the switch below is disconnected. When low-power output is required, the opposite is true. Compared with OC or OD, such a push-pull structure has high and low-level drive capabilities. If two output ports of different levels are connected together, a large amount of current will be generated, and the output ports may be burned out. The OC or OD output mentioned above will not be like this, because the current provided by the pull-up resistor is relatively small. If the push-pull output is to be set to a high-impedance state, the two switches must be disconnected at the same time (or use a transport door on the output port), which can be used as the input state, some IO ports of the AVR Microcontroller are in this structure.

 

Characteristics and Application of Open leakage Channels

In circuit design, we often encounter the concepts of open drain and open collector.

The "drain" mentioned in the so-called open-leakage circuit concept refers to the drain pole of the MOs. Similarly, the "set" in the open set circuit refers to the collector of the transistor. An on-line leakage circuit refers to a circuit with extremely high output of the MOs. In general, the pull-up resistance is added to the circuit with an external leakage pole. The complete open-leakage circuit should be composed of an Open-leakage device and an open-leakage pull-up resistor. 1:

Figure 1

Circuit components have the following characteristics:

1. Use the drive capability of the external circuit to reduce the internal drive of the IC (or the load driving voltage higher than the chip supply voltage ). When the internal MOS of the IC are turned on, the driving current is from the external VCC flowing through the R pull-up, the MOs to GND. The IC only needs a very low gate drive current. 1.

2. You can connect multiple Pin pairs with open/missing output to an online line. Form a "logical" relationship. 1. When any one of PIN_A, PIN_ B, and PIN_C gets low, the logic for online exposure is 0. This is also the principle that I2C, SMBus, and other bus determine the bus occupation status. If it is used as the output, it must be connected to the pulling resistance. When the capacitive load is connected, the descent delay is the transistor in the chip, which is the active drive and the speed is fast. The Descent delay is the passive external resistance, and the speed is slow. If the speed and high resistance are required, the power consumption will be high. Therefore, the choice of load resistance should take into account both power consumption and speed.

3. You can change the transmission level by changing the voltage of the pull-up power supply. 2. The logic level of the IC is determined by the power supply vcc1. the output high level is determined by the Vcc2 (the power supply voltage of the pull-up resistor. In this way, we can use the low-level logic to control the output High-Level Logic (so that you can perform any level conversion ). (For example, the TTL/CMOS level output can be provided by adding a pull-up resistor .)

Figure 2

4. when the Open-drain Pin is not connected to the external pull-up resistor, it can only output a low level (therefore, for the P0 port of the classic 51 single-chip microcomputer, an external pull-up resistor is required for the input/output function, otherwise, the High-Level Logic cannot be output ). In general, open-drain is used to connect devices of different levels.

5. The standard opening and dropping feet generally only have the output capability. Only by adding other judgment circuits can two-way input and output capabilities be achieved.

6. The normal CMOS output level is the upper and lower two tubes. Remove the above pipes as OPEN-DRAIN. This output has two main purposes: level conversion, line and.

7. the cables and functions are mainly used when multiple circuits are used to pull down the same signal. If the current circuit does not want to pull down, It outputs a high level because the pipe above OPEN-DRAIN is removed, high level is achieved by external pull-up resistance. (For a normal CMOS output level, if one output is high or the other is low, it is equal to a short circuit of the power supply .)

8. Open-drain provides a flexible output mode, but it also has its weakness, that is, the delay of the rising edge. Because the rising edge is charged by the external pull passive resistance, the latency is small when the resistance is selected, but the power consumption is large; otherwise, the delay is large and the power consumption is small. Therefore, if you have requirements for latency, we recommend that you use the descent edge output.

Note:

1. The principle of open-circuit and open-circuit is similar. In many applications, we use open-circuit to replace open-circuit. For example, an input pin must be driven by an open-leakage circuit. The common driving method is to use a transistor to form an open circuit to drive it, which is convenient and cost-effective. 3.

2. The R pull-up resistance determines the speed of the logical level conversion. The higher the resistance, the lower the speed and power consumption. And vice versa.

The push-pull output is generally called the push-pull output. It should be more suitable than the CMOS output in the CMOS circuit, because the push-pull output capability in the CMOS cannot be as large as the bipolar. The output capability depends on the area of the N-tube p-tube output in the IC. Compared with the open-drain output, the level of push-pull is determined by the IC power supply, and logical operations cannot be performed simply. Push-pull is the most widely used output-level design method in the Current CMOS circuit.

Of course, open drain does not have no cost, that is, the output drive capability is poor. The output driving power is not accurate. The driving power depends on the last transistor power in the IC. The OD only brings the delay of the rising edge, because the rising edge is charged by the external pull passive resistance, when the resistance is selected for an hour, the delay is small, but the power consumption is large, and the delay is large, the power consumption is small. Open drain provides a flexible output mode, but it also has a cost. If you have requirements on latency, we recommend that you use a descent edge output.

The precondition for low latency of resistance is that the principle of resistance selection should be within the allowable range of power consumption of the last-level transistor. When experienced designers use a logical chip, the 1 ohm resistor is not selected as the pull-up resistor. When the rising edge power of the pulse is charged to the load by pulling the passive resistance, the lower the resistance, the shorter the rising time. In the falling edge of the pulse, apart from the discharge of the load through the active transistor, the power supply also forms a path through the uplink resistor and the on-going transistor, resulting in the power consumption and power consumption of the chip. The resistance affects the rising edge without affecting the falling edge. If you do not care about the rising edge during use, you can select as much as possible to reduce the local path current. If the requirement for the rising time is high, the selection of the resistance should be based on the chip power consumption.