Digital Power Supply Design Based on tms320f28044

Digital Power Supply Design Based on TMS320F28044

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Source: Today's electronics/21IC Author: Cai Liang, an engineer at wenting Digital System (Beijing) Co., Ltd.

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What is a digital power supply? TI defines digital power supply in terms of functions: digital power supply is a digital control power supply product, which can provide management and monitoring functions and extend to the control of the entire circuit. For applications in different fields, TI has released a variety of DSP processors that can implement digital power products, such as the TMS320F280x series, TMS320F2801x series, and a 16-channel high-precision pwm dsp processor, TMS320F28044. In systems that require a large number of DC channels, it is very easy to design a digital power supply with 28044. a dsp can control up to 16 DC channels, and the output voltage can be freely programmable, it greatly enhances the flexibility of the power supply system, and the power supply system will become very intelligent and controllable. This article mainly discusses how to design multi-channel DC/DC power supply based on TMS320F28044.

System Framework
Figure 1 shows the multi-channel DC/DC Digital Power System Framework Based on C2000DSP. the topology of DC/DC is generally a typical BUCK circuit or a Synchronous BUCK circuit, the output voltage is directly sent to the ADC port of the DSP after being sampled by the resistor network. The DSP samples the value internally and then compares it with the given value, the error value after comparison passes through the PID mediation to obtain the duty cycle of each channel, so that each BUCK circuit forms a closed loop system. At the same time, some peripheral interfaces such as RS232 and I2C can exchange data with the host computer through these interfaces, or follow the PMBUS protocol through the I2C interface to form an intelligent digital power supply system.

High Precision PWM

Figure 1 C2000-based digital DC/DC system framework

The TMS320F28044 provides up to 16 high-precision PWM waves. Theoretically, the PWM wave can obtain a resolution of up to 10 ns at a clock speed of MHz. However, as a DC/DC converter, if you want to obtain a DC output voltage with high precision and low ripple, higher switching frequency and higher PWM resolution are required. A micro-edge controller is provided inside the TMS320F28044, which can output a PWM with a minimum of PS. The system clock speed is 100 MHz, the PWM wave frequency is 200 kHz, and the duty cycle needs to output 50.1%. If only the ordinary PWM wave output is used, the cycle value is set to 5000, the COMPA value is set to 250, and the maximum is 2500 ns. The duty cycle is 50%, set to 251, and the duty cycle is 50.2%. So how can we obtain a duty cycle close to 50.1% to the maximum? This requires a high-precision PWM wave. The COMPA value is set to 250, and then the 5ns high level needs to be generated, CMPAHR is set to 32, 32 × 150 = 4.8ns, duty cycle is 50.096%, CMPAHR is set to 150 × 50.099% = 4.95ns, duty cycle is 150, CMPAHR is set to 34,34 × 50.102% = 5.1ns, duty cycle is, it can be seen that when CMPAHR is set to 33, the error of duty cycle is only 0.001%. If High Precision PWM wave is not used, the error is 0.1%. It can be seen that the error can be reduced by two orders of magnitude by using a high-precision PWM wave. If it is used to control the digital power supply, it can greatly improve the control precision of the digital power supply.

BUCK loop topology

Figure 2 BUCK-based digital control Topology

Figure 2 shows the DC/DC Digital Control topology based on the BUCK circuit. Q1, diode, L, C, and R constitute the BUCK type converter, and the output voltage is converted to 0 ~ through the conditioning circuit ~ The voltage signal of 3 V is sent to the internal ADC of the DSP. After comparing the output of the ADC with the reference voltage, the error signal E is obtained. E is then obtained by the Controller GC of the voltage loop, and the adjusted duty cycle U of the BUCK mediation device is obtained, U is used as the computing factor output by the PWM module in the chip to generate the PWM signal for the corresponding duty cycle. The PWM signal is then driven by the power switch through the driving circuit to obtain the expected output voltage. The entire process is controlled by a number inside the DSP. By setting the appropriate PID parameters, good dynamic characteristics can be obtained.

Digital sampling

Figure 3 digital sampling principle of DC/DC Converter

The selection of sampling time in digital control is of great significance to the control policy. Figure 3 shows how to properly set the conversion time of the ADC in the DC/DC converter to obtain accurate sampling values. The comparison register of T1 can be used to store the duty cycle of the PWM wave to be generated. By changing the value of the comparison register, the PWM wave with the expected duty cycle can be obtained. In this example, the conversion trigger of the control register setting of the ADC occurs in the middle of the rising edge of the ADC, that is, the intermediate time of the switch on-going. After the ADC is converted, an interruption is triggered, in the interrupt service subroutine, the user program reads the AD conversion result from the ADC result register, executes the digital controller, and updates the output duty cycle of the PWM wave, the New PWM wave takes effect in the next cycle. As shown in figure 3, the Controller completes the PWM wave update to the next ADC interrupt trigger. There is a lot of idle time in the middle, which means that if the system has enough bandwidth, you can add more controllers to control multiple DC/DC converters. Other user programs such as communication can be executed in the Background Loop.

PID Control
The digital power development kit provided by TI contains the controller algorithm macro. In the ControlLawMacro. h header file, this macro is based on a 2 P/2Z transfer function:

The expression for PID discretization is as follows:

2 P/2Z transfer function:

It can be seen that PID is only a special case of 2 P/2Z, A1 =-1 and A2 = 0
The PID coefficient is as follows:
Coef2P2Z_1 [0] = Dgain * 67108 // B2
Coef2P2Z_1 [1] = (Igain-Pgain-Dgain) * 67108 // B1
Coef2P2Z_1 [2] = (Pgain + Igain + Dgain) * 67108 // B0
Coef2P2Z_1 [3] = 0; // A2
Coef2P2Z_1 [4] = 67108864; // A1
Coef2P2Z_1 [5] = Dmax [1] * 67108; // Clamp Hi limit (Q26)
Coef2P2Z_1 [6] = 0x00000000; // Clamp Lo
You can define or change Pgain, Igain, and Dgain to adjust the control algorithm. In order to facilitate debugging, the above parameters can be made into a progress bar in CCS, and the system can be debugged in real time by moving the progress bar.

Software Framework
Software Framework 4.

Figure 4 software framework

Design instance
As shown in Design Example 5, this design has the following features:

Figure 5 design an instance

● Use the Child Board and mother board connection method
● The Sub-board is based on the TMS320F28044 controller.
● The motherboard contains 10 typical BUCK circuits, with the maximum load current of each circuit being 1A
● Any voltage software is programmable and the programming range cannot exceed 5 V
● The reference voltage can be dynamically changed
● The system's PID parameters can be dynamically changed to debug the system's Dynamic Performance
● Can be configured with high precision PWM and general PWM output.