Dm8168 bumpy hardware path (ddr3)

A new 8168 board was created. During ddr3 debugging, emif0 encountered an error in some data bits.

Ddr3 128 MB * 8 = 1 GB

To test all the space of ddr3, I save the address to ddr3, which is the operation of * pdata ++ = (uint32) pdata.

The following problem occurs:

Write 80000000 from 0x80000000, write 80000004 from 0x80000004, and so on

Run at full speed. Check the memory in the memory browser after writing all the files and find the problem:

The original 80000000 saved in 0x80000000 is changed to 88000000, and 80000004 is changed to 88000004.

That is, the data bit d [27] is changed from 0 to 1.

I went on to test. This time I changed to * pdata ++ = ~ (Uint32) reverse operation of pdata

Run at full speed. After writing all the data, let's take a look back:

The original 7 fffffff stored in 0x80000000 is changed to 77 ffffff, and the 7 ffffffb in 0x80000004 is changed to 77 fffffb.

At this time, the data bit d [27] is changed from 1 to 0...

This error always occurs in emif0, and emif1 does not.

When I write data to the memory in a single step of CCS, I observe that the memory is correct data. The above problem does not occur, or I only write a small part of the memory.

And the full speed operation does not have the above problem, that is, after writing a large amount of data and running at full speed, 100% will have this 27th data flip situation, which should have been

Is 1 to 0, it should be 0 to 1...

My idea is that the ddr3 with the highest data bit in the emif0 part of the 8-piece ddr3 has a problem, and the performance is not good. Do you want to change it?

If this is the case, it will be too bad luck. The cost of the board is very expensive. This BGA blow welding hand is shaking. I'm dizzy. If you have other possible reasons, please advise.

Dm8168 bumpy hardware path (ddr3)