DM8168 Dmm/tiler Introduction (good) __ Embedded

Http://www.cnblogs.com/pengkunfan/p/3746635.html
DM8168 Dmm/tiler Introduction 1. Overview

As figure 4-1,dmm positioned at the front end of the SDRAM controller, it is the memory access interface generated by all initiator.

Dynamic memory Manager DMM, is a specialized management module, broadly speaking, including all aspects of memory access.  For example: Initiator The priority of indexing is generated. Multi-area SDRAM memory interleaving configuration block target transmission optimization: tiling and sub-tiling set low delay page translations: similar to MMU

Memory dynamic management performance is software configurable, nature for Run-time, the DMM operation of memory management has 4 aspects: Add initiator priority to any input request to perform tiled request tiling conversion provides optimized low latency based on page translation to manage memory fragmentation: MMU Distribute traffic between two memory controllers in a interleaved configuration.

Tiler is a child module within DMM to efficiently manipulate 2D data, such as HDVICP2 video/image access by using the tiled format. Optimize management of memory fragmentation and achieve 0 copy physical frame buffering through page-granularity translations. Generates a high speed 0 waste transformation: 90/180/270 rotation, with horizontal or vertical mirrors.

2. Feature latency particularly low interconnect ports: ELLA, the DDR data for cortex A8 access between the two EMIF bank can be interleaved, using programmable, multi-area DRAM memory mapping, which increases the memory pass rate by twice times, Supports up to 4 separate memory regions (section) programmable initiator, up to 16 initiator groups, based on the priority request extension. Supports address translation of tiled data, using Pat in 4KB page granularity, which helps manage memory fragmentation. 2 Internal Address lookup tables (LUT), each with 256x128 entry and 4 refill engines for programming luts with automatic synchronous reload. Supports 4 separate Pat Windows. 3. Function Module Diagram

Figure 4-2 shows the DMM macro structure. The DMM consists of 6 modules: The PEG: a priority extension generator, which is used to generate the priority required by the SDRAM controller. Note that these priorities are not used in DMM. ELLA: Very low latency access, it has its own interconnect from the port, which is used to provide very low latency access to memory. LISA: Local interconnect and synchronization agent for synchronizing all DMM subsystems and providing access to configuration registers. PAT: Physical Address translation, used to manage memory fragmentation. ROBIN: The reset buffer and Intiator nodes, a total of 2, have their own interconnected master ports, which are used to make requests to the SDRAM controller, allowing tiled data, tiled response, and split response refactoring, The Robin module can only manage the reset buffer and data redirection required by the execution data due to orientation. Tiler:2, which has its own interconnect from the port, used to convert requests between the input virtual address mode and the output physical tiled address. Note that the tiling request conversion, write data and response are performed entirely by the Tiler module,

4. Some key words and abbreviations

Bpp:bits per pixel the number of digits used for each pixel

Dmm:dynamic Memory Manager Dynamic memory management

Ella:extra Low latency access to extreme base latency

Gb,gib:both imply Giga byte is the meaning of gigabytes

Initiator: A node in a device that can be a CPI, peripheral, or DMA, which may be the internal Bus manager (MASTER). Each initiator is identified by a connid (connection ID connection ID), Connid the maximum limit is 16, some initiator are grouped together, and a connid number is used.

Interlaced:qualifier for access skipping one line every line can hop interleaved access

Iva:image Video Accelerator, Also called HDVICP2, IVA_HD image Accelerator, also known as HDVICP2,IVA_HD

Lisa:local Interconnect and synchronisation agent local interconnect and synchronization agent

Kb,kib:both imply Kilo byte is thousand-byte meaning

Lut:look Up Table lookup tables

Mmu:memory Management Unit Memory snap-in

Mpu:main processing Unit. For the Device, it is cortex A8 Master processor, this refers to cortex A8

Pat:physical addresses Translator Physical Address translation

Peg:priority Extension Generator Priority extension Generator

Progressive: In contrast to interlaced, a line of continuous access is required.

Robin:re-ordering buffer and Initiator node re-ordered buffers and initiator nodes

Tiled access: 1D or 2D access to the tiled area. Here, the image is read and written in 2D mode. Improved 2D access efficiency, such as macro block access to images, Tiler simplified to a simple 1D linear read and write request, DMM is responsible for completing the address read and write specified in the request in contiguous memory.

2d ACCESS:HDVICP2 and HDVPSS can generate a special access to the 2D image cache with read/write requests, height and width information. Dmm-tiler is based on the height width and address to decode the access type, responsible for reading/writing data to physical memory, based on the granularity of tile coordinates.

http://blog.csdn.net/shanghaiqianlun/article/details/762048

Hdvpss using TI developed algorithm, flexible composite and fusion engine, a variety of high-quality external video interface to achieve video/image display and acquisition processing functions.

2.1.3 Abbreviations

Name	Defined
COMP	Compositor	Compounding device
DEI	De-interlacer	Go to interlaced
Deih	High quality De-interlacer	High quality to Interlace
DVO	Digital Video Output	Digital Video output
Grpx	Graphics Pipeline	Graphic water
HD	High Definition	Hd
Hdcomp	High Definition Component	HD Component
Hdmi	High Definition Multimedia Interface	HDMI interface
Hdvpss	High Definition Video Processing subsystem	HD Video Processing Subsystem
Nf	Noise Filter	Noise filtering
Ntsc	National Television System Committee	Ntsc
Pal	Phase Alternating Line	Pal
Sc	Scaler	Scaling
Sd	Standard Definition	Sd
Sdk	Software Development Kit	Software Development Kits
Tiler	Tiling and isometric Light weight Engine for rotation	Tile and equal volume lightweight rotary engine
Venc	Video Encoder	Video Signal Modulation encoder
Vip	Video Input Port	Video Input port