(Electrician base note) Introduction to the production of FPGA engineering with Vivado

1. Do a stopwatch example today to introduce the FPGA project with Vivado

2. Use two keys key0(stopwatch drive, pause),key1

The following demonstrates the Vivado operation Process

1.create Project(figure)

2. It is usually selected (figure)

3. do not select source files (figure)

4. Select the chip (we use the xc7a35tftg256-1) can also use filters to select the chip (figure)

5. Click Finish, our project is created, but a blank, we will eventually produce a bit file (figure)

We can see the information window,summary window etc.

6.Add Source(figure)

7. Add the design source file first (figure)

8. The documents we want have been written, top.v, keys.v, CNT.V

Cnt is a counter,keys is to shake (implemented with timed sampling) (figure)

Add 3 source files in turn, click OK directly

9. Set as top-level file (figure)

10. Copy the existing source code in

11. We also need to constrain the file, on the one hand to have timing constraints, but also pin assignment Z

Blank Add source->add or creat constraints->name (master generally takes this name )

In the future, we have been using the teacher to provide the . xdc file just fine. (For pin assignment)

Figure

Note, however, that the pin assignment for theDDR is not in the . Xdc file

How do I release the commented out pin? Ctrl +'?/'

important !!! Suppose you have an output ABC, you want to put ABC somewhere (extended I/O port)

You can take the note out and change the get_port back to 'ABC' .

Figure

It's equivalent to putting ABC on that I/O .

When we want to save,Vivado checks for syntax errors, ignore:

Figure

13.vivado Simple Analysis of the structure of the . V

Figure

14. We click generate Bitstream(figure)

We can also focus on the message window (figure)

The compilation is complete, we can look at the various reports inside implementation

Download to the board, we should open the Hardware Managerdirectly, the Development Board power

Open New target->next-> can look inside the monitor (figure)

1. Download the bit file (figure)

Figure

Must be careful . RUNS/IMPL_1/TOP.V

after downloading, the temperature drops sharply (the. V file is simpler)(figure)

Note: After power-down, the project will return to its original appearance! Because there is no cure works!

In the next section I will describe how to complete the Vivado cure to SPI Flash

(Electrician base note) Introduction to the production of FPGA engineering with Vivado