Embedded System Basics

1, the definition of embedded system

(1) Definition: application-centric, computer-based, software and hardware can be cut to adapt to the application system to function, reliability, cost, volume, power consumption requirements of the dedicated computer system.
(2) 4 stages of embedded system development: No operating system stage, simple operating system stage, real-time operating system stage, Internet-facing stage.
(3) Intellectual property core (IP Core): With intellectual property rights, functional specific, interface specification, can be reused in multiple integrated circuit design function module, is the realization of the system chip (SOC) of the basic components.
(4) The IP Core module has the behavior, the structure and the physical 3 level different degree design, corresponding describes the function behavior the difference may divide into three kinds: soft core, solid core, hard core.

2, the composition of embedded system

Includes: hardware layer, middle layer, system software layer and application software layer (1) hardware layer: Embedded microprocessor, memory, universal Device interface and I/O interface.

Embedded Core Module = microprocessor + Power circuit + clock circuit + memory
Cache: Located between main memory and embedded microprocessor cores, storing the most recent program code and data used by microprocessors. Its main goal is to reduce the memory access bottleneck caused by the memory to the microprocessor core, making processing faster.
(2) The middle layer (also known as the hardware Abstraction Layer HAL or the Board Support package BSP).

It separates the upper system software from the underlying hardware, so that the system's upper-level software developers do not need to relate to the underlying hardware, and can be developed based on the interface provided by the BSP layer.
There are two features of BSP: hardware affinity and OS affinity.
Designing a complete BSP requires two parts of the work:
A, the embedded system hardware initialization and BSP function.
Chip-level initialization: pure hardware initialization process, the embedded microprocessor from the default state of power-up is gradually set to the operating state required by the system.
Board-level initialization: The initialization process, which includes both hardware and software, establishes the hardware and software operating environment for subsequent system initialization and application.
System-Level initialization: a software-based initialization process that initializes the operating system.
B, design hardware-related device drivers.
(3) System software layer: composed of RTOs, file system, GUI, network system and general component module.

RTOs is the foundation and development platform of embedded application software.
(4) application software: composed of applications developed based on real-time systems.

3. Real-time system

(1) Definition: A system capable of completing system functions and responding to external or internal, synchronous or asynchronous times within a specified or determined time.
(2) Difference: General system generally pursues the average response time of the system and the user's convenience, while the real-time system mainly considers the worst-case system behavior.
(3) Features: Time constraint, predictability, reliability, and interaction with the external environment.
(4) Hard Real Time (strong realtime): Refers to the application of time requirements should be able to be fully satisfied, otherwise it will lead to major security incidents, and even caused significant loss of life and property and ecological damage, such as: aerospace, military.
(5) Soft real-time (weak real-time): refers to some applications although the time requirements, but the real-time task of occasional violations of this demand on the system operation and environment will not have serious impact, such as: monitoring system, real-time information acquisition system.
(6) Constraints on tasks include: time constraints, resource constraints, execution order constraints, and performance constraints.

4, the real-time system scheduling

(1) Scheduling: Given a set of real-time tasks and system resources, determine when and where each task executes the entire process.
(2) Preemptive scheduling: Typically a priority-driven dispatch, such as Ucos. The advantages are good real-time, fast response, relatively simple scheduling algorithm, can guarantee the time constraints of high-priority tasks, the disadvantage is that the context switch more.
(3) Non-preemptive scheduling: Usually a schedule that is allocated on a time slice, does not allow the task to be interrupted during execution, and once the task occupies the processor it must be executed or voluntarily discarded, such as wince. The advantage is that the context switch is less, the disadvantage is that the processor effective resource utilization is low, the scheduling is not good.
(4) Static table driving strategy: According to the time constraint and correlation relation of each task, the system uses some search strategy to generate a running timetable, indicating the starting running time and running times of each task.
(5) Priority-driven policy: determines the order in which tasks are executed according to the priority of the task.
(6) Real-time task classification: Periodic tasks, occasional tasks, non-cyclical tasks.
(7) The general structure model of real-time system: Data Acquisition task realizes the collection of sensor data, data Processing task processing and the processing data sent to the Executing agency Management task Control agency execution.

5, embedded microprocessor architecture

(1) von Neumann structure: The program and data share a storage space, program instruction store address and data storage address point to the same memory different physical location, with a single address and data bus, the program and data width is the same. For example: 8086, ARM7, MIPS ...
(2) Harvard structure: The program and data is two independent memory, each memory independent address, independent access, is a program storage and data storage separate memory structure. For example: AVR, ARM9, ARM10 ...
(3) Comparison of the characteristics of CISC and RISC. The
time required for the computer to execute the program can be calculated using the following formula:
P=ixcpixt
I: The number of instructions that are run on the machine after the high-level language program compiles.
CPI: The average number of cycles required to execute each instruction.
T: The time of each machine cycle.
(4) Pipeline idea: In the CPU, the serial execution of an instruction into several instructions of the sub-process in the CPU overlap execution.
(5) Pipeline indicator:
Throughput Rate: The number of results from the pipeline processing machine in unit time. If the sub-process of the pipeline takes a different amount of time, the throughput rate should be the inverse of the oldest process.
Settling time: The time at which the pipeline begins to work to the maximum throughput rate. If the time of the M-sub-process is the same as T, then the time T=MT is established.
(6) The byte order of the information store
A, Memory units: bytes (8 bits)
B, Word length determines the addressing capability of the microprocessor, that is, the size of the virtual address space. The virtual address space bit 232 of the
C, 32-bit microprocessor, or 4GB.
D, small-endian byte order: Low byte at low memory address, high byte at high memory address.
E, Big endian byte order: High byte at low memory address, low byte at high memory address.
F, the storage order problem of network devices depends on the data link layer in the underlying OSI model.

6, Logic circuit Basics

(1) According to whether the circuit has a storage function, the logic circuit is divided into: combinational logic circuit and sequential logic circuit.
(2) combinational logic circuit: The output of the circuit at any one time depends only on the input signal at that moment, regardless of the state of the circuit before the input signal is acting. The common logic circuit has the decoder and the multi-channel selector and so on.
(3) Sequential logic circuit: the output at any time of the circuit is not only related to the input at that moment, but also to the state of the circuit at that moment. Therefore, a memory element must be included in a sequential circuit. A trigger is the basis for a sequential logic circuit. The commonly used sequential logic circuits include registers and counters.
(4) Truth table, Boolean algebra, Morgan's law, gate circuit concept. The
(5) nor (or non) and NAND (and non) gate circuits are called all-in-one gates and can implement any kind of logic function.
(6) Decoder: A multi-input multi-output combined logical network.
One n-bit binary code per input, with a maximum of one valid on the M-output.
When the m=2n is, is fully decoded, and when m<2n, is partially decoded.
(7) because the high-level output current of the integrated circuit is small, and the low-level output current is relatively large, the use of integrated gate circuit directly drive the LED, more low-level drive mode. The LCD seven-segment character display LCD uses a liquid crystal with an applied electric field and different optical characteristics to display characters without an applied electric field. The
(8) clock signal is the basis of the temporal logic that determines the appropriate update of the State in the logical unit. Synchronization is the main constraint in the clock control system.
(9) When the trigger is selected, the trigger mode is a factor that must be considered. There are two kinds of triggering methods:
Level triggering: a simple structure, often used to form a scratchpad.
Edge Trigger mode: Has a strong anti-data interference ability, often used to form registers, counters and so on.

7, bus circuit and signal driver

(1) bus is a set of various signal lines, is the embedded system in the transmission of data, address and control information between the public access. At the same time, one binary signal can be transmitted on each path line. According to the type of information transmitted by the bus, it can be divided into: Data bus (DB), address bus (AB) and Control Bus (CB).
(2) Main parameters of the bus:
Bus bandwidth: The amount of data that can be transmitted on the bus over a certain period of time, usually expressed in mbyte/s.
Bus width: The number of data bits (bit) that the bus can transmit simultaneously, that is, the concept of 32-bit, 64-bit bus width, also known as the bus bit width. The wider the width of the bus, the higher the bus data rate per second, that is, the wider the bus bandwidth.
Bus frequency: The operating clock frequency in MHz, the higher the operating frequency, the bus will work faster, that is, the wider bus bandwidth.
Bus bandwidth = Bus bit width x bus frequency/8, in Mbps.
Common bus: ISA bus, PCI bus, IIC bus, SPI Bus, PC104 bus and can bus, etc.
(3) Only devices with three-state output can be connected to the data bus, the commonly used three-state gate is the output buffer.
(4) When the load on the bus exceeds the load capacity of the bus, it is necessary to add a buffer or a driver between the bus and the load, the most commonly used is a tri-state buffer, its role is to drive and isolate.
(5) Using the bus multiplexing technology can realize the common use of the data bus and the address bus. But there are two questions:
A, the need to increase the external circuit to the bus signal multiplexing decoupling, such as: address latch.
B, bus speed relative to the non-multiplexed bus system is low.
(6) Two types of bus communication protocol: Synchronous mode, asynchronous mode.
(7) The solution to the problem of bus arbitration is based on the concept of priority (priority).

8. Level conversion Circuit

(1) Digital integrated circuits can be divided into two main categories: Bipolar integrated Circuit (TTL), Metal oxide Semiconductor (MOS).
(2) CMOS circuit is widely used because of its low static power consumption, high working speed and strong anti-jamming ability.
(3) To solve the TTL and CMOS circuit interface difficult method is the TTL circuit between the output and the power supply of a pull-up resistor R, pull-up resistor R value is determined by the TTL high-level output leakage current IOH, different series of TTL mayors with different R values.

9, Programmable logic device Foundation

This aspect of the content, from the overall concept of a sense of understanding should be possible.

10. Information Representation and Operation Foundation in embedded system

(1) Carry count system and conversion: This is relatively simple, but also should master how to convert, there is the possibility of a question.
(2) The representation of the number in the computer: source code, anti-code and complement.
The inverse code of positive numbers is the same as the source code, minus the inverse code for the number of the source code in addition to the symbol bit-based negation.
The complement of positive numbers is the same as the source code, and the complement of negative numbers is added to the inverse code of the number.
For example-98 source: 11100010B
Anti-code: 10011101B
Complement: 10011110B
(3) fixed-point notation: The position of the decimal point of the number is fixed by the artificial agreement.
Floating point notation: The decimal point position of the number is floating, which consists of the part of the tail and the order of the digits.
Any binary N can always be written as: N=2pxs. S is the mantissa and P is the order number.
(4) Chinese character notation, make clear gb2318-80 Chinese standard Code and machine code transformation.
(5) Speech coding waveform quantization parameters (may be a simple calculation of the problem OH)
Sampling frequency: The number of samples in one second, reflecting the size of the interval between sample points.
The hearing limit for the ear is 20kHz, so the sampling frequency above 40kHz is enough to satisfy the person.
CD discs use a sampling frequency of 44.1kHz.
Measurement accuracy: Sample quantification level, the current standard sampling magnitude of 8-bit and 16-bit two.
Number of channels: mono and stereo dual channel. Stereo requires twice times more storage space.

11, error control code

(1) According to the function of the code group, can be divided into two types of error detection code and correction code. Error detection code refers to the code that can automatically detect errors, such as parity code, error correction code is not only can detect errors and can automatically correct the error code, such as cyclic redundancy check code.
(2) Parity code, SEA-plaintext, cyclic redundancy check code (CRC).

12. Measurement project of embedded system

(1) Performance index: Divided into Parts performance index and comprehensive performance index, mainly include: throughput rate, real-time and various utilization.
(2) Reliability and safety
Reliability is the most important and outstanding basic requirement of embedded system, and it is a guarantee of the normal work of an embedded system, which is usually measured by MTBF of mean time interval.
(3) Maintainability: Generally with mean repair time mttr expressed.
(4) Availability
(5) Power consumption
(6) Environmental adaptability
(7) Versatility
(8) Security
(9) Confidentiality
(10) Scalability
Cost-effective price, in addition to direct purchase of embedded system prices, should also include installation costs, a number of years of operating maintenance costs and software rental fees.

13. Evaluation method of embedded system: Measurement method and Model method

(1) Measurement method is the most direct and basic method, need to solve two problems:
A, according to the purpose of the study, determine the system parameters to be measured.
B. Select tools and methods of measurement.
(2) There are two ways of measuring: Sampling mode and event tracking mode.
(3) Model method is divided into analysis model method and simulation model method. Analysis model method is to use some mathematical equations to describe the model of the system, and the simulation model method is to use the simulation program to dynamically express the state of the embedded system, and the system statistical analysis, to obtain performance indicators.
(4) The most used model in the analytic model is the queueing models, which consist of three parts: input stream, queue rule and service organization.
(5) using the model to evaluate the system needs to solve 3 problems: Design model, Solution model, calibration and verification model.

Interface Technology 1. Flash memory

(1) Flash memory is a non-volatile memory, according to the different structure can be divided into nor flash and NAND flash two kinds.
(2) Features of flash Memory:
A, block structure: physically divided into a number of blocks, the blocks are independent of each other.
B, First wipe write: Flash write operations can only be written to the data bits from 1 to 0, cannot be written from 0 to 1, so before writing to the memory must first perform the erase operation, the pre-written data bits are initialized to 1. The minimum unit of the erase operation is a chunk, not a single byte.
C, Operation instructions: Perform a write operation, it must enter a series of special instructions (NOR Flash) or complete a time series (NAND Flash) to write data.
D, bit reversal: Due to the intrinsic nature of Flash, in the reading and writing process occasionally produces one or several bits of data errors. Reversal cannot be avoided, and the results can only be dealt with afterwards by other means.
E, bad block: Once the block is damaged, it cannot be repaired. The result of a corrupted chunk operation is unpredictable.
(3) NOR Flash Features:
The application can run directly in flash memory without having to read the code into the system RAM. NOR Flash has high transmission efficiency and is highly cost-effective in 1MB~4MB small capacity, but very low write and erase speeds greatly affect its performance.
(4) Features of NAND Flash
The ability to increase extremely high density cells can achieve high storage density, and the speed of writing and erasing is fast, which is why all USB drives use NAND flash as storage media. The difficulty of applying NAND flash is that flash memory requires a special system interface.
(5) NOR Flash and NAND flash difference:
A, NOR flash read faster than NAND flash a bit faster.
B, NAND Flash erase and write faster than nor flash much faster
C, NAND Flash random reading ability, suitable for a large number of continuous reading data.
D, NOR Flash with SRAM interface, there are enough addresses to address the introduction, it is easy to access its internal every byte. NAND Flash addresses, data, and commands share a 8-bit bus (with a write company's product using 16-bit), and each read and write uses a complex I/O interface to sequentially access data.
E, NOR flash capacity is generally small, usually between 1MB~8MB, NAND Flash is used only in 8MB or more products. Therefore, NOR Flash applies to the data store as long as it is applied to the code storage medium.
F, the maximum number of erase times per block in NAND Flash is 1 million, and nor Flash is 100,000 times.
G, NOR Flash can be connected like other memory, very direct use, and can run directly on the code, NAND Flash requires a special I/O interface, in use, you must write to the driver before you can continue to perform other operations. Because designers cannot write to bad blocks, this means that virtual images must be performed throughout NAND flash.
H, NOR Flash for the data reliability requirements of the code storage, communication products, network processing and other fields, is a code flash, NAND Flash is used for high storage capacity requirements of MP3, memory card, u disk and other fields, is becoming a data flash.

2. Ram Memory (1) Features of SRAM:

SRAM represents a static random access memory, as long as the power supply it will maintain a value, it does not have a refresh cycle, the trigger constitutes a basic unit, low integration, each SRAM storage unit consists of 6 transistors, so its cost is higher. It has a high rate and is commonly used in high-speed buffer memory.
There are typically 4 types of pins in SRAM:
CE: Chip selection signal, low level active.
R/W: Read and write control signals.
Address: A set of addresses lines.
Data: A set of bidirectional signal lines for data transmission.
(2) Characteristics of DRAM:

DRAM represents dynamic random access memory. This is a semiconductor memory stored in the form of an electric charge. Each of its storage units consists of a transistor and a capacitor, and the data is stored in the capacitor. The capacitance is lost due to electrical leakage, so the DRAM device is unstable. It must be refreshed regularly to keep the data in memory.
The DRAM interface is more complex and usually has a pin:
CE: Chip selection signal, low level active.
R/W: Read and write control signals.
RAS: The line address is a pass-through signal that is usually connected to the high-level part of the address.
CAS: A column address is a pass-through signal, usually a low part of the address.
Address: A set of addresses lines.
Data: A set of bidirectional signal lines for data transmission.
(3) features of SDRAM:

SDRAM means synchronous dynamic random access memory. Synchronization refers to the memory work requires synchronous clock, internal command sending and data transmission is based on it, dynamic refers to the memory array needs constant refresh to ensure that the data is not lost. It usually only works at the 133MHz frequency.
(4) Characteristics of Ddram

The Ddram represents a double-rate synchronous dynamic random access memory, also known as DDR. Ddram is based on the SDRAM technique, SDRAM transmits data only once in a clock cycle, it transmits data during the rise of the clock, and DDR memory is transmitted two times in a clock cycle, it can transmit the time of the clock's rise and fall. At the 133MHz frequency, the DDR memory bandwidth can reach 133x64b/8x2=2.1gb/s.

3, hard disk, compact disc, CF card, SD card

4. Gpio principle and Structure

A GPIO is the most basic form of I/O, which is a set of input pins or output pins. Some Gpio pins can be programmed to change direction of operation, usually with two control registers: data register and Data Direction register. The data direction register sets the direction of the port. If the pin is set to output, then the data register will control the PIN state. If the pin is set to input, the state of this input pin is controlled by the logic circuit layer on the pin.

5. A/D interface

(1) A/D converter is a circuit that converts an electric analogue into a digital quantity. There are many methods to realize A/D conversion, and the common methods are counting method, double integral method and successive forcing method.
(2) Counting type A/D conversion method
Its main circuit components include: Comparator, counter, D/a converter and standard voltage source.
It works simply to say that there is a counter, starting from 0 to add 1 count, each time plus 1, the value as input to the D/a converter, which produces a comparison voltage VO compared to the input analog voltage vin. If Vo is less than VIN continue to add 1 count until Vo is greater than vin, then the value of the counter is the output of the A/D converter.
This conversion mode is characterized by simple, but slower speed, especially when the analog voltage is higher, the conversion speed is slower. For example, for a 8-bit A/D converter, if the input analog is the maximum value, the counter will be counted from 0 to 255, do 255 d/A conversion and voltage comparison work to complete the conversion.
(3) Double-integral A/D conversion method
Its main circuit components include: integrator, comparator, counter and standard voltage source.
Its working principle is that the circuit to input the voltage to be measured at a fixed time of integration, and then the standard voltage for the fixed slope of the reverse integration, the reverse integration to a certain time, then return to the starting value. Because of the fixed slope, the time to reverse integrate the standard voltage is proportional to the input analog voltage value, the greater the input analog voltage, the longer the reverse integration back to the starting value. As long as the standard high-frequency clock pulse to determine the time spent on the reverse integration, you can obtain the corresponding input analog voltage of the digital amount, also completed A/D conversion.
Its characteristic is, has the very strong anti-interference ability of the power frequency, the conversion precision is high, but the conversion speed is slow, usually the conversion frequency is less than 10Hz, mainly uses in the digital test instrument, the temperature measurement and so on aspect.
(4) Successive approximation type A/D conversion method
Its main circuit components include: comparator, D/a converter, successive approximation register and voltage reference.
Its working principle is, essentially is the sub-search method, and the usual balance of the use of the same principle. In the A/D conversion, the D/a converter increases the conversion bit by bit from high to low, produces different output voltages, and compares the input voltage to the output voltage. First make the highest bit 1, which is equivalent to removing the reference voltage of 1/2 compared to the input voltage, if the input voltage is less than 1/2 of the reference voltage, then the highest position 0, and vice versa 1. Then, the secondary high position 1, the equivalent of 1/2 in the range of sub-search, and so on, successive approximation.
Its characteristics are fast, high conversion accuracy, the n-bit A/D converter only need M clock pulse can be completed, generally can be used to measure the transition process of dozens of to hundreds of microseconds changes, is currently the most commonly used conversion method.
(5) An important indicator of a/D conversion (it is possible to test some simple calculations)
A, resolution: reflects the A/D converter's ability to respond to a small change in input, usually expressed as the level value of the analog voltage corresponding to the digital output minimum bit (LSB). An n-bit A/D converter can reflect the analog input level of the 1/2n full scale.
B, Range: can be converted to the analog input voltage range, divided into unipolar and bipolar two types.
C, conversion time: The time required to complete A/D conversion, the countdown to the conversion rate.
D, accuracy: accuracy and resolution are two different concepts, even if the resolution is very high, it may be due to temperature drift, linearity and other reasons to make its accuracy is not high enough. The precision has the absolute precision and the relative precision two kinds of expression method. Absolute precision is typically represented by a fraction of the least significant bit LSB of the digital value, and the relative accuracy is expressed as a percentage of the analog voltage full scale.
For example, full-scale 10v,10 bit A/d chip, if its absolute accuracy is ±1/2LSB, then its least significant bit LSB quantization unit is: 10/1024=9.77MV, its absolute precision is 9.77MV/2=4.88MV, relative precision is: 0.048%.

6, D/a interface basic

(1) d/A converter enables the conversion of digital quantities to analog quantities.
(2) in the integrated circuit, the T-type network is usually used to convert the digital to analog current, and then by the OP amp to convert the analog circuit to analog voltage. The d/A conversion actually requires the above two links.
(3) The classification of D/a converters:
A, voltage output type: Often used as high-speed D/a converter.
B, current output type: General external op amp is used.
C, multiplication type: can be used as a modulator and the input signal to be digitized attenuation.
(4) d/A converter main indicators: resolution, settling time, linearity, conversion accuracy, temperature coefficient.

7. Keyboard interface

(1) Two types of keyboard: linear keyboard and Matrix keyboard.
(2) There are two ways to identify closed keys on a keyboard: line scan and line reversal.
(3) Line scanning method is commonly used for matrix keyboard keys recognition method, this method is divided into two steps:
A, the key to identify which column of the keyboard is pressed: let all lines are low, query the line level is low, if there is a low column, then the column has a button is pressed, otherwise no key press.
B, if a column has a key press, identify which row of the keyboard is pressed: line down, and the rest of the high level of behavior, query the changes of the columns, if the column level becomes low, you can determine this row this column intersection button is pressed.

8. Display Interface

(1) The basic principle of LCD is to control the passage of light through the power supply to different liquid crystal units, so as to achieve the purpose of display.
(2) There are two ways to provide the light source of LCD: projective and reflective type. The LCD display of the notebook computer is a projection type, and there is a light source behind the screen, so the external environment can not need the light source. The LCD used on the general microcontroller is reflective, requiring the outside world to provide power, by reflecting light to work. Electroluminescence (EL) is a way for the LCD to provide a light source.
(3) According to the LCD drive classification, the common LCD can be divided into three categories: torsional column (TN), ultra-twisted nematic (STN) and thin-film transistor type (TFT).
(4) There are two types of LCD in the market: LCD display module with drive circuit, as long as bus mode, no driver circuit LCD display, using controller scanning mode.
(5) Normally, when the LCD controller works, through the DMA request bus, directly through the SDRAM controller to read the specified address in SDRAM (display buffer) data, this data through the LCD controller converted to the LCD screen scan data format, direct drive LCD display.
(6) The VGA interface is essentially an analog interface, generally using a unified 15-pin interface, including 2 NC signals, 3 display data bus, 5 GND signal, 3 RGB color components, 1 line synchronization signal and a field synchronization signal. The level standard used for its color component is the RS343 standard defined by EIA.

9. Touch Screen Interface

(1) According to the principle of work, touch screen can be divided into: surface acoustic wave screen, capacitive screen, resistive screen and several infrared screen.
(2) Touch screen control using a professional chip, such as ADS7843.

10. Audio Interface

(1) Basic principle: the data of the microphone input is decoded by the audio codec to complete A/D conversion, the decoded audio data through the audio controller into the DSP or CPU for the corresponding processing, and then the data through the audio controller sent to the audio encoder, encoded D/a converted by the speaker output.
(2) The format of digital audio has a variety of, the most commonly used is the following three kinds:
A, digital audio (PCM): is the data format used for CDs or DVDs. Its sampling frequency is 44.1kHz. With a precision of 16 bits, the PCM audio data rate is 1.41mb/s and 2.42 MB/s when the precision is 32 bits. A 700MB CD can hold approximately 60 minutes of music in a 16-bit PCM data format.
B, MPEG Layer 3 Audio (MP3): The audio format used by the MP3 player. The stereo MP3 data rate is 112kb/s to 128kb/s.
C, ATSC digital audio compression standard (AC3): Digital TV, HDTV and film digital audio encoding standard, stereo AC3 encoded data rate of 192kb/s.
(3) IIS is a commonly used serial audio digital interface for encoding or decoding audio data. The IIS bus processes only sound data, and other control signals need to be transmitted separately. IIS uses 3 serial buses: Data line SD, field selection line WS, Clock signal line sck.
(4) When the data field width of the receiver and sender is different, the sender does not take into account the data field width of the receiving party. If the sender sends a data field that is less than the width of the system field, it is 0 lower, and if the sender's data width is greater than the receiver's width, the portion that exceeds the LSB is truncated. The field selection WS is used to select the left and right channels, ws=0 means to select the Ieft channel, and Ws=1 to select the channel. In addition, WS enables the receiving device to store the previous byte and is ready to receive the next byte.

11. Serial Interface

(1) Serial communication refers to the communication that enables the data to be transmitted one by one. Compared with the parallel communication, serial communication has the advantages of less transmission line and low cost, especially suitable for long distance transmission, and the disadvantage makes the speed slow.
(2) Serial data transmission has 3 basic modes of communication: simplex, half-duplex, full duplex.
(3) Serial communication can be divided into 2 ways in the Information format: synchronous communication and asynchronous communication.
A, asynchronous transmission: each character as a separate message to transmit, and according to a fixed and predetermined timing of transmission, but between the characters are dependent on the character and the character of any timing. When asynchronous communication occurs, the characters are transmitted one frame at a time, and each frame of the character is transmitted by the starting bit to synchronize. The interval between each code of a frame of data is fixed, and the time interval of two adjacent frames is not fixed.
B, synchronous Transmission: Synchronization is not only between the characters are synchronized, and the timing between the characters and characters is still synchronous, that is, the synchronization method is to ****** many characters into a character block, before each piece of information to add one or two synchronization characters, Word converts sequential blocks and then add the appropriate error detection data to be sent out.
(4) Asynchronous communication must follow 3 rules:
A, character format: Start bit + data + Check bit + stop bit (check bit can not), low first transmission.
B, baud rate: the number of bits transmitted per second.
C, check bit: parity.
A, odd check: to make the word multibyte Colonel has an odd number of "1".
B, even test: to make the word multibyte Colonel has an even number of "1".
(5) Electrical characteristics of rs-232c: negative logic.
A, on TXD and Rxd: Logic 1 is -3v~-15v, logic 0 is 3v~15v.
B, in TEs, CTS, DTR, DCD and other control lines:
Signal valid (on state) is 3v~15v
Invalid signal (off state) is -3v~-15v
(6) The level conversion between the TTL standard and the RS-232C standard is realized using the integrated chip RS232.
(7) RS-422 Serial Communication Interface
A, RS-422 is a single-unit transmission, multi-machine receive one-way, balanced transmission specifications, transmission rate of up to 10mb/s.
B, RS-422 using differential transmission, also known as balanced transmission, using a pair of twisted pair.
C, RS-422 need a terminal resistor, the resistance is about equal to the characteristic impedance of the transmission cable.
(8) RS-485 Serial Bus interface
A, RS-485 is established on the basis of RS-422 standards, increased multi-point, two-way communication capacity, communication distance of dozens of meters to thousands of meters.
B, RS-485 transceiver with balanced transmission and differential reception, with the ability to suppress common mode interference.
C, RS-485 requires two terminal resistors. The terminal resistor is not required for transmission at close range (300m).

12. Parallel Interface

(1) The data transmission rate of the parallel interface is 8 times times faster than the serial interface, the standard parallel interface data transmission rate is 1mb/s, commonly used to connect printers, scanners, etc., so also known as the print port.
(2) The parallel interface can be divided into SPP (standard concurrent port), EPP (enhanced parallel port) and ECP (extended type).
(3) Parallel bus is divided into standard and non-standard two classes. Common parallel standard buses are the IEEE 488 bus and the ANSI SCSI bus. Mxi bus is a kind of high performance non-standard universal multiuser parallel bus.

13. PCI Interface

The

(1) PCI bus is the high-performance 32-bit and 64-bit bus for address and data multiplexing, and is the interconnection mechanism between the microprocessor and the peripheral control components and the peripheral add-on board.
(2) from the data width, PCI defines a 32-bit data bus and can be extended to 64 bits. From the bus speed, there are two kinds of 33MHz and 66MHz.
(3) compared with ISA bus, the PCI bus address bus and data bus time-sharing, support Plug and Play, interrupt sharing and other functions.

14, USB interface

(1) The main features of the USB bus:
A, easy to use, Plug and Play.
B, each USB system has a host, this USB network can be connected to a maximum of 127 devices.
C, a wide range of applications to support the simultaneous operation of multiple devices.
D, low-cost cables and connectors with a unified 4-pin plug.
E, strong error correction ability. The low protocol overhead of
F brings high bus performance and is suitable for the development of low-cost peripherals.
G, support for majority and multi-message flow between hosts and devices, and support for synchronous and asynchronous transport types.
H, bus power supply, can provide 5v/100ma power to the equipment. The
(2) USB system is described by 3 parts: USB host, USB device, and USB interconnect.
(3) USB bus supports 3 kinds of data transmission rate: high-speed signaling bit transfer rate is 480mb/s, full-speed signaling bit transfer rate is 12mb/s, full-speed signaling bit transfer rate is 1.5mb/s. The
(4) USB bus cable has 4 wires: a pair of twisted-pair signal lines and a pair of power cords.
(5) USB is a query bus that initiates all data transfers by the host controller. The peripherals attached to the USB share the USB bandwidth via a token-based protocol that is scheduled by the host.
(6) Most bus transactions involve the transmission of 3 packets:
A, token package: Indicates what transaction to perform on the bus, the USB device to be addressed, and the direction of data transfer.
B, packet: Transmits data or indicates that it has no data to transmit.
C, handshake Package: Indicates whether the transfer was successful. The USB data transfer model between the
(7) host and the device endpoint is called a pipe. There are two types of pipelines: streams and messages. The message data has a USB-defined structure, and the data stream does not. The
(8) Transaction Schedule table allows for flow control of some stream pipelines, at the hardware level, by using a nak (deny) handshake signal to adjust the data transfer rate to prevent overflow or underflow from the buffer. The most important feature of the
(9) USB device is Plug and play.
(10) How it works: When a USB device is plugged into a USB endpoint, the host communicates with the device's endpoint 0 through the default address 0. In this process, the host sends out a series of standard requests that attempt to get descriptors, through which the host obtains all of the device information that is of interest, thus knowing the device's situation and how it communicates with the device. The host then sets a unique address for the device by issuing a set address request. In the future, the host communicates with the device by setting a good address for the device, instead of using the default address 0.

15, SPI Interface

The

(1) SPI is a synchronous protocol interface where all transmissions refer to a common clock, which is generated by the host and the peripheral that receives the data uses the clock to synchronize the reception of the serial bit stream.
(2) When multiple devices are connected to the same SPI interface of the host, the host is selected from the device's chip selector pin.
(3) SPI mainly uses 4 signals: Host output/Slave input (MOSI), host input/slave output (miso), serial clock SCLK and peripheral chip select CS. The
(4) host and peripheral contain a serial shift register that initiates a data transfer by writing a byte to its SPI serial register. The registers transmit bytes to the peripheral through the MOSI signal line, and the peripherals return the contents of their shift registers to the host via the miso signal line, so that the contents of the two shift registers are exchanged.
(5) when the write and read operations of the peripheral are synchronized, the SPI becomes a very effective protocol.
(6) If only a write operation is performed, the host simply ignores the bytes received, and conversely, if the host reads a byte from the peripheral, it must send an empty byte to raise the slave's transmission.

16, IIC interface

(1) IIC Bus is a high-performance multi-host bus with bus arbitration and high-speed equipment synchronization and other functions.
(2) The IIC bus requires two lines: Serial data line SDA and serial clock line SCL.
(3) Each device on the bus has a unique address for identification, and each device can be used as a transmitter or receiver (determined by the function of the device).
(4) IIC Bus has 4 modes of operation: Primary send, main receive, send from, receive from.
(5) IIc in the transmission of data process ****** there are 3 types of signals:
A, start signal: SCL is low, SDA from high to low jump change.
B, End signal: SCL is low, SDA from low to high jump change.
C, the response signal: the receiver after receiving 8 bits of data, the 9th pulse to the sender of the low-level characteristics.
(6) After the main device sends a start signal, it also immediately sends out a slave address to notify the slave device that it will be communicating with. The 1-byte address includes the 7-bit address information and the 1-bit transmit direction indication bit, if the 7th bit is 0, which indicates that a write operation is to be performed, or 1, indicating that a read operation is to take place.
(7) The length of each byte transmitted on the SDA line is 8 bits, and there is no limit to the number of bytes per transmission. The first byte after the start signal is the Address field, followed by an answer bit (ACK) after each transport byte, and the MSB (Byte high) of the serial data in transit is sent first.
(8) If the data receiver is unable to receive more data, it can interrupt the transmission by keeping the SCL low, which forces the data sender to wait until the SCL is released again. This allows high-speed device synchronization to be achieved.
(9) The working process of IIC Bus: SDA and SCL are both bidirectional. When idle, both SDA and SCL are high, only SDA becomes low, then the SCL becomes low, and the data transfer of the IIC bus begins. Each of the transmitted on the SDA line is sampled on the rising edge of the SCL, and the bit must remain valid until the SCL becomes low again, and SDA transmits the next bit before the SCL becomes high again. Finally, the SCL goes back high, and SDA goes high, indicating the end of the data transfer.

17. Ethernet Interface

(1) The most commonly used Ethernet protocol is the IEEE802.3 standard.
(2) Transmission codes (both 06 and 07 are ******): Manchester code and differential Manchester code.
A, Manchester code: There is a level change in the middle of each, from the high to the end of the jump to indicate "0", from low to high jump is expressed as "1".
B, differential Manchester code: There is a level change in the middle of each bit, using the start of each code element has no jump to indicate "0" or "1", there is a jump to "0", no jump to "1".
(3) In contrast, the Manchester coding code is simple and the differential Manchester code provides better noise rejection performance.
(4) Ethernet Data transmission characteristics:
A, the transmission of all data bits starts from low, and the transmitted bit stream is encoded in Manchester.
B, Ethernet is a bus multiplexing method based on conflict detection, which is executed automatically by hardware.
C, the transmitted data length, the destination address da+ Source address sa+ Type field type+ data segment data+ pad pad, the minimum is 60B, the maximum is 1514B.
D, usually Ethernet card can receive data of 3 kinds of address: broadcast address, multicast address, own address.
E, the physical address of any two network cards are different, is the only one in the world, the network card address is allocated by the specialized agencies.
(5) There are two implementations of the embedded Ethernet interface:
A, embedded processor + network card chip (for example: Rtl8019as, CS8900, etc.)
B, processor with Ethernet interface.
(6) TCP/IP is a layered protocol, divided into: physical layer, Data link layer, network layer, Transport layer and application layer. Each layer implements a clear function that corresponds to one or several transport protocols, each of which is implemented as a separate packet relative to its lower layer. The protocols on each tier are as follows:
A, Application layer: BSD sockets.
B, Transport layer: TCP, UDP.
C, Network layer: IP, ARP, ICMP, IGMP
D, Data link layer: IEEE802.3 Ethernet MAC
E, physical layer: binary bit stream.
(7) ARP (Address Resolution Protocol)
A, the network layer uses a 32-bit address to identify different hosts (that is, IP addresses), and the link layer use a 48-bit physical address (MAC) to identify different Ethernet or token network interfaces.
B, ARP function: To achieve the conversion from the IP address to the corresponding physical address.
(8) ICMP (Network Control Message Protocol)
A, the IP layer uses it to exchange error messages and other important control information with other hosts or routers.
B, the ICMP message is transmitted within the IP packet.
C, the Network diagnostic Tool Ping and traceroute is actually the ICMP protocol.
(9) IP (Internet Protocol)
A, IP work in the network layer, is the TCP/IP protocol family the most core protocol.
B, all TCP, UDP, ICMP, and IGMP data are transmitted in the IP packet format.
C, TTL (Time-to-live field): Specifies the time to live the IP packet (the number of routers that the packet can pass through).
D, IP provides unreliable, non-connected packet delivery service, efficient and flexible.
A, unreliable: it does not guarantee that packets will reach their destination successfully, and any required reliability must be provided by the upper layer (e.g. TCP). In the event of an error, IP has a simple error-handling algorithm-discarding the packet and sending an ICMP message to the source end.
b, no connection: IP does not maintain any status information about subsequent packets. The processing of each packet is independent of each other. IP packets can be received out of order,
(ten) TCP (Transmission Control Protocol)
The TCP protocol is a reliable connection-oriented transport layer protocol that provides high-reliability end-to-end data communication for two hosts.
(one) UDP (User Packet protocol)
UDP protocol is a non-connection unreliable Transport layer protocol, it does not guarantee that the packet can reach the destination, the reliability has the application layer to provide. The UDP protocol is less expensive and more suitable for applications in low-end embedded areas than TCP.
(12) Port: TCP and UDP use 16-bit port number to identify the upper level of the user, that is, the application layer protocol, such as the TCP port number of the FTP service is the TCP port number of the 21,telnet service is the UDP port number of the 23,TFTP service is 69.

18. Can bus interface

(1) CAN (Control area network, controller LAN) bus is a multi-master mode of serial communication bus, is one of the most widely used fieldbus, was initially used in the automotive environment of the electronic control network. In a single network composed of a can bus, it is ideal to hook up any number of nodes, and the node data in practical application is limited by the electrical characteristics of the network hardware. The
(2) bus signal is transmitted using a differential voltage. Two signal lines are called Can_h and can_l, Static is about 2.5V, at this time the state represents logic 1, also can be called "recessive". The logic 0, called "dominant", is represented by Can_h higher than can_l, at which point the voltage is usually can_h=3.5v and can_l=1.5v.
(3) when the "dominant" and "recessive" bits are sent simultaneously, the last bus value will be the "dominant" feature which lays the foundation for the arbitration of Can bus. The
(4) One bit time of the can bus can be divided into 4 parts: The synchronization segment, the propagation time period, the phase buffer Segment 1 and the phase buffer segment 2. The data frame of the
(5) Can bus is available in two formats: standard format and extended format. Includes: Frame Start, arbitration field, control field, data field, CRC field, Ack field, and frame end. The
(6) Can bus hardware interface includes: Can bus controller and can transceiver. The can controller mainly completes the work of timing logic conversion, such as Philip's SJA1000. The can transceiver is the physical layer chip of the can bus, enabling the conversion of TTL level to the can bus level characteristics, such as TJA1050.

19, xDSL interface

(1) XDSL (Digital subscriber line) technology is, in the existing users on both sides of the telephone line access to a dedicated DSL modem equipment, on the user line using digital digital signal high frequency bandwidth of the characteristics of a wide range of direct digital signal transmission, eliminating the intermediate A/D conversion, Break through the analog signal transmission limit rate of 56kb/s idle. The
(2) DSL technology is mainly divided into two categories: symmetric and asymmetric. The
(3) is more suitable for enterprise point-to-point connection applications, such as file transfer, video conferencing and so on the same amount of data.
(4) ASDL is another broadband access technology developed in recent years, which uses twisted-pair copper wire to provide the user with a two-direction rate asymmetric broadband information service.
(5) ADSL on a pair of telephone lines simultaneously transmit a high-speed downlink data, a low rate upstream data, one analog phone. Frequency division multiplexing is used in different frequency bands to transmit voice in low frequency band, uplink channel data and control information are transmitted in the middle narrow band, and the remaining high frequency bands transmit downlink channel data, image or high-speed data.