Emi clock design

During the hardware design of the product, EMI should be considered at the beginning of the design to reduce the financial and human resources required for subsequent rectification.

This paper uses the clock signal as an example to design EMI to reduce radiation interference.

 

(1) Schematic Design

1. the power supply of the clock chip is separated from other power sources by magnetic beads. The decoupling capacitor is added after the magnetic beads. The decoupling capacitor is composed of 22uf's ta capacitor and 0.1 UF, 0.01 UF, and UF's porcelain capacitor, these capacitors can filter noise at different frequencies. Generally, 22uf is applicable to noise below 10 MHz, and 0.1uf is applicable to noise between 5 MHz and 5 MHz ~ 66 MHz, 0.01uf for 40 MHz ~ 80 MHz and 0.001uf are suitable for higher-frequency noise. As shown in the following figure, the capacitor can be adjusted according to the actual usage.

Figure 1 decoupling capacitor of the clock chip

 

2. On the clock signal line, source impedance matching is usually required, for example, 33r matching resistance. At the same time, after matching resistance, add a 3 ~ 5 pf capacitor, for a clock with a frequency lower than MHz, add a 10 ~ 15 pF capacitor, forming an RC Filter, inhibiting high-frequency radiation of more than MB. Increasing R and C reduces EMI radiation, but the clock waveform also deteriorates.

Figure 2 clock Line Processing

 

(2) PCB design

1. The power supply decoupling capacitor of the clock chip should be placed as close as possible to the power supply pin of the chip.

2. Try to control the number of holes in the clock line. Generally, no more than two holes are allowed.

3. If there is a hole in the clock line, you can add a bypass capacitor in the adjacent position of the passing hole to ensure that the current loop of the reference layer (adjacent layer) is continuous after the switching layer of the clock line. For example:

Figure 3 bypass capacitor at the Pass hole

4. In principle, no cross-island clock lines are allowed. When the clock frequency is high, if it is not cross-island, you can place a 0.1uf capacitor near the clock line between the two islands to form an image path.

5. The clock line should be far away from other signal lines. It is best to handle it in a package.

6. Try to keep the up/down clock resistor close to the clock chip.

7. When winding, the incoming line and outgoing line should be as far as possible.