Emosyn tt120 chip migration

Author: scruffybear

Release time: 19/06/2007

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In the first two months, I migrated the emosyn TP series chip COs to the tt120 chip. I feel that these two chips, which are the same as emosyn, are still quite different. Aside from all the details, for the single chip type, the TP series chip is the EEPROM chip, and the emosyn tt120 chip is a flash chip. The following describes some main features of the tt120 chip.

Addressing Mode
We will be the whole Chip address space called NVM, user can configure space called UCM, TP100-2 as an example, it has 98k NVM space, of which 66k UCM and 32 k eeprom. Tt120 has a 120k NVM, which is also a 120k UCM. The disposable space is clear, and the rest is how to access and read the chip space.
Both the TP series and tt120 are 8051 cores. The memory control of the TP series chip is to allocate space through the MMU device. Through the "Code banking" mechanism, in bank0, bank1, bank2, switch between bank3 to access more than 64 K space. That is to say, all address spaces can be accessed through two-byte dptr.
The tt120 chip does not have an MMU device, but it supports a 24-bit addressing mode, that is, "24-bit contiguous addressing mode". Sorry, I don't know how to translate "contiguous. The 24-bit addressing mode can address 16 m space, while tt120 only has K flash space, so you can access all the space without using the MMU device, in addition, it is a bit "small-sized", and there will be more room for use in the future for larger-capacity smart cards.
The 24-bit addressing mode is also called the extended addressing mode. in the 16-bit addressing mode of assembler languages, dptr is composed of two registers: DPH and DPL. If it is a 24-bit extended addressing mode, dptr consists of three registers: DPX, DPH, and DPL. The three registers can be used as a 24-bit operation.
If you need to use the 24-bit addressing mode, you need to make relevant settings in the Keil compiling environment to support the extended addressing mode, under the "project"-"options for target 'tt120 '"-"device" menu, as shown in red circles in 1, you must replace the bl51 connector with the lx51 connector, the ax51 assembler must be used to replace the A51 assembler.

Figure 1
Under the "project"-"options for target 'tt120 '-" target "menu, you need to select" contiguous mode: 512kb program "because our program size is much smaller than 512 KB, therefore, do not select the 16 M mode. In addition, select "'far' memory type support", as shown in figure 2.

Figure 2
In C51, the 24-bit addressing mode corresponds to the far remote type pointer. with the definition of the far type pointer, the address space of 16 MB can be accessed. In fact, our cos only takes into account the 16-bit address mode in 8051-Core scenarios. For address spaces that exceed 64 KB, the extended block addressing mode is used for operations, that is, the "block number + offset" method.
Now the question is: how to migrate from the 16-bit addressing mode of the TP series to the 24-bit addressing mode of the tt120 series. Another saying is that the original Access Base zone can use two bytes, currently, three bytes are required to access the basic area (because the code is put before the basic area ). Should we use far type pointers in C51. The answer is no. Because the modification to the original system should be minimized during the chip migration process, that is, the 16-bit addressing mode should be used in the C51, exceeding the address space of 64 KB, use the extended area operation (also a 16-bit address ).
To address the 24-bit address space with a 16-bit address, you can use the base address method. When addressing a K flash Address, the upper layer uses two-byte dptr and dptrw to convert them to three-byte dptr and dptrw for underlying read/write. In the program, eepbase must be added to all the addresses in the basic zone, and eepbase must be subtracted after use. Extbase must be added to all the addresses in the extended zone. after use, extbase must be subtracted. For SRAM, xrambase must be added to all the addresses, and xrambase must be subtracted after use.
Although it is difficult to implement this method, this method is only used to ensure compatibility with the original COs and minimize changes.
Page erasure Mode
The chip is used to store information. In the final analysis, it is composed of binary values 1 and 0. There is no problem with reading the chip and it is easy to understand, but it is troublesome to write the chip. The binary data stored in the chip can only be written as 0, but not 1. the binary data stored in the chip must be written as 1 and erased. Therefore, when writing a byte to the chip, we must first erase the byte (if necessary, that is, 0 must be written as 1) and then perform the write operation.
However, there is a difference in the chip erase granularity. Taking the TP series EEPROM chip as an example, you can erase at least 8 bytes each time. For the tt120 flash chip, you can only erase at least 256 bytes each time.
For the TP Series, to write one of the eight bytes, all the eight bytes must be erased (if necessary), and the adjacent bytes are erased before writing. So here we introduce the concept of backup. We will first back up 8 bytes, operate on the backup area, erase 8 bytes, and then write back the backup area. This achieves the goal of writing one byte. The same is true for writing a string of data.
The same is true for tt120 write operations, but the backup size has changed. Each time 256 bytes are backed up, 256 bytes are erased each time. This is similar to Samsung's c9dd, but c9dd is not the core of 8051.

Batch script debugging environment
There is no hardware simulation for the TP series and tt120 of emosyn, and it can only be simulated using pure software. This brings great pain to the programmer's debugging, because in the serial port input window of Keil integration, it cannot be pasted, copied, or rolled back, and only one character can be entered at a time, if the input is incorrect, enter all the data again. In addition, software simulation is not reliable and stable. Debugging is similar to chronic suicide.
In the tt120 project, the debugging environment configuration for batch processing scripts is performed, simulating serial port input for batch data.

Figure 3
Keil UV3 integrates a tool for batch script processing, but requires subsequent development and configuration.
As shown in figure 3, you need to program the apdu_test.ini file.
Defines the semaphores function, signal void apdutest (void) and signal void apdutest_reset (void), and loops in these two functions, the content in the array of apdu_command_buffer [] and apdu_command_buffer1 [] is processed to process serial input in large batches.
The last two buttons are defined:
Define button "apdutest", "apdutest ()"
Define button "apdutest_after_reset", "apdutest_reset ()"

You can use these two buttons to start the semaphore function to simulate a large number of input to the serial port.

The apdu_command_buffer [] and apdu_command_buffer1 [] arrays are defined in the apdu_test.h file. The apdu_test.h file is introduced by the timecosc. c file. The format of apdu_test.h is as follows:
Code apdu_command_buffer [] =
{
0xa0, 0x20, 0x00, 0x0b, 0x08, 01,
0x36, 0x34, 0x37, 0x32, 0x32, 0x32, 0x38, 0x38, 02, // a020000b0836343732323838sw9000
};
Code apdu_command_buffer1 [] =
{
0xa0, 0x10, 0x00, 0x00, 0x14, 01,
}

The simulation is as follows (Figure 4 and figure 5 ):

Figure 4

Figure 5
Several important abbreviations:

MMU Memory Management Unit
NVM non-volantile memory
UCM user retriable memory