ep3c16q240c8n Pin Description

Power supply and reference pins

Vccint:
Type: Power
Function: Core voltage 1.2v/5%. Responsible for powering the internal logic array supply pins.
Pin: A total of 12 pins, including: 10, 40, 53, 61, 74, 115, 129, 140, 163, 190, 204, 228.

VCCIO[1..8]:
Type: Power
function: I/O supply voltage, a total of 8 blocks, each block supply voltage is different, support all I/O input and output standards. Drive JTAG Ports (TMS, TCK, TDI, and TDO) and the following pins: Nconfig, DCLK, data[15..0], NCE, Nceo,nwe, Nreset, NOE, Flash_nce, NCSO and CLKUSR.
Pin: A total of 16 pins, including: 7, (BANK1), 35, (BANK2), 66, (BANK3), 96, 104 (BANK4), 124, 136 (BANK5), 154, (BANK6); 192, 206 (BANK7) ; 213, 225 (BANK8).

GND:
Type: Ground
function: All GND pins of the device should be connected to the board floor.
Pin: A total of 27 pins, including: 11, 16, 36, 42, 48, 54, 62, 67, 75, 79, 97, 105, 116, 125, 130, 138, 141, 156, 165, 172, 191, 193, 205, 208, 215, 227, 229.

Gnda:
Type: Ground
Function: The ground of the PLL. Need to connect with GND.
Pin: Total includes 4 pins, GNDA1 179 (GNDA2) 2 (GNDA3) 122 (GNDA4).

VREFB[1..8]N[0..2]:
Type: I/O
function: Reference voltage PIN power supply. To input a reference voltage for each block, if a block uses a reference voltage as the I/O port standard, the reference voltage pin corresponding to the block needs to be connected to the power supply. If not, then direct grounding.
Pin: A total of 16 pins, including: 13, 39, 76, 114, 139, 169, 184, 223 (vrefb1n0~ vrefb8n0); 22, 46, 63, 107, 133, 161, 195, 235 (vrefb1n1~ vrefb8n1).

VCCA[1..4]:
Type: Power
Function: Power supply to phase-locked loop analog power supply and other analog devices, 2.5V.
Pins: A total of 4 pins, including: 58, 178, 3, 123 (VCCA1~VCCA4).

VCCD_PLL[1..4]:
Type: Power
Function: PLL Digital supply voltage, 1.2V.
Pin: A total of 4 pins, 60, 180, 1, 121 (VDD_PLL1~VDD_PLL4).

RUP[1..4]:
Type: I/o,input
Function: (multiplexing function PIN) chip upper connection (OCT) reference pin block I/O group 2,4,5, and 7. If used, the external must be connected to the precision resistor, not when the normal I/O port (temporarily not, do not delve into).
Pin: Includes 4 pins: 51, 111, 126, 187 (RUP1~RUP4).

Dedicated Configuration/jtag Pin

DATA0:
Type: Input (ps,fpp,as) bidirectional Open Drain (AP)
Function: Dedicated configuration input pin. In serial configuration mode, the bit-width configuration data is received through this pin. In the as mode, there is a pull-up resistor inside the DATA0 and is always valid. As configured, the DATA0 is a dedicated user-controllable input pin. DATA0 is used as a PP or PS configuration and can be used as I/O, the status of the pin depends on the two pin settings. After the AP is configured, the DATA0 is a dedicated user-controllable, fixed-bidirectional pin.
Pin: Total 1 feet, 24.

MSEL[3..0]:
Type: Input
Function: Configuration pin for setting Cyclone III configuration scheme. These pins must be hardware connected to VCCA or GND. Some of the smaller devices and packages in Cyclone III do not support AP flash programming and do not have mesl[3] feet.
Pins: Total 3, 155, 157, 158 (MSEL0~MSEL2)

NCE:
Type: Input
Function: Dedicated chip enable foot, low level active. When the nce is low, the device is enabled and the device is disabled when the NCE is high.
Pin: Total 1, 30.

Nconfig:
Type: Input
Function: Dedicated high-configuration control input. Pulling down this pin in user mode loses the FPGA configuration data and goes into the reset state, and all I/O ports become tri-State (high-impedance state). When this pin becomes high, it is reconfigured. The buffer on this pin supports hysteresis and can be used with Schmitt trigger.
Pin: Total 1, 25.

Conf_done:
Type: bidirectional (open drain)
Features: Dedicated configuration status pins. The output status. Before configuration and configuring the device Conf_done should be driven to a low level. Once all the configuration data has no errors, the initialization cycle begins and Con_done is released. As an input state, Con_done receives all the data and becomes high. The device then initializes and enters user mode.
Pin: Total 1, 153.

Nstatus:
Type: bidirectional (open drain)
Features: Dedicated configuration state feet. After powering on the FPGA and releasing it after the POR time (power off), the drive Nstatus is immediately low. As an output state, when an error occurs during configuration, the Nstatus is pulled low. As an input state, an error occurs when the Nstatus is pulled down externally during configuration and initialization. (during initialization and configuration, this call is in the input state, do not pull down!) ）
Pin: Total 1, 17.

TCK:
Type: Input
Function: Jtag dedicated input pin, the TCK is connected to the ground, JTAG circuit is forbidden.
Pin: Total 1, 27.

Tms:
Type: Input
Function: Jtag dedicated input pin, the TMS connected to VCC (+ 3.3v), Jtag circuit is forbidden.
Pin: Total 1, 28.

Tdi:
Type: Input
Function: Jtag dedicated input pin, the TDI connected to VCC (+ 3.3v), Jtag circuit is forbidden.
Pin: Total 1, 26.

TDO:
Type: Output
Function: JTAG dedicated output pin.
Pin: Total 1, 29.

Clock and phase-locked loop pins

CLK[0,2,4,6,9,11,13,15], Diffclk_[0..7]p:
Type: Clock,input
function: Dedicated global clock input pin, can also be used for differential global clock input of the positive end or user input pin. Differential P.
Pin: (CLK0), CLK2 (CLK4), (CLK6), (CLK9), 212 (CLK11), (CLK13), and (CLK15).

CLK[1,3,5,7,8,10,12,14], Diffclk_[0..7]n:
Type: Clock,input
function: Dedicated global clock input pin, can also be used for differential global clock input of the negative end or user input pin. Differential N.
Pin: (CLK1), CLK3, 151 (CLK4), 149 (CLK7), 209 (CLK8), 211 (CLK10), (CLK12), (CLK14).

Pll[1..4]_clkout[p,n]:
Type: I/o,output
function: I/O pins can be used as two single-ended clock outputs or a differential clock output pair. If he has a PLL push output, these pins can only use the differential I/O standard.
Pins: A total of 8, 4 differential pairs, respectively: 69,70 (PLL1_CLKOUTP,PLL1_CLKOUTN), 185,186 (PLL2_CLKOUTP,PLL2_CLKOUTN), 239,240 (pll3_clkoutp,pll3 _CLKOUTN), 117,118(PLL4_CLKOUTP,PLL4_CLKOUTN).

Optional/multiplexed Configuration pins

DCLK:
Type: Input (PS,FPP) i/o,output (AS,AP)
Function: Configure the clock pin. In PS and PP configuration modes, the DCLK is the configuration data from the external element to the Cyclone III device. In the AS and AP modes, the DCLK is the output of the Cyclone device that configures the interface to provide timing. After the AP is configured, the change pin can be used as user-selectable user control for I/O pins.
Pin: Total 1, 23.

Nceo:
Type: I/o,output
Function: When the setting is complete, the output drive is pulled low.
Pin: Total 1, 162.

FLASH_NCE,NCSO:
Type: I/o,output
Function: The function of this pin is flash_nce in AP mode and behaves as NCSO in as mode. There is a pull-up resistor inside the pin and is always valid. NCSO: In serial configuration (as) mode, the device can be configured from the output control signal of the Cyclone III device to the configuration device. Flash_nce: In AP mode, from the Cyclone III device output control signal to parallel flash, enable flash.
Pin: Total 1, 14.

DATA1,ASDO:
Type: Input (FPP) Output (AS) bidirectional Opne-drain (AP)
Function: This pin is DATA1 in PS,FPP,AP mode and is ASDO in as mode. DATA1: In non-as mode, as data input pin. Send full-byte or word-width data to the target device via data[7..0] or data[15..0]. In the PS configuration scenario, the DATA1 as the user's I/O pin, is tri-state. After the FPP is configured, as the user I/O foot, the state of the foot depends on the dual-use pin setting. After the AP is configured, the DATA1 is a dedicated bidirectional user-selectable pin. ASDO: Used in as mode to read data by controlling the signal of Cyclone III to the configuration device. In the as mode, this ASDO pin has an internal pull-up resistor, which is always valid. After the as configuration, the pin is a user-selectable pin that is dedicated to the output.
Pin: A total of 1, 12 feet.

DATA[7..2]:
Type: Input (FPP) bidirectional opne-drain (AP)
Function: Data entry. Send all-byte or full-width data via data[7..0] or data[15..0] to the target device. In the configuration of as or PS, in the configuration process, the role of user I/O, that is, three-state (high-impedance state). After the configuration of the AP, data[7..2] is dedicated to bidirectional user-selectable pins.
Pins: 218, 219, 221, 226, 231, 232 (data2~ DATA7).

DATA[15..8]:
Type: Bidirectional Opne-drain (AP)
Function: Data entry. Send all-byte or full-width data via data[7..0] or data[15..0] to the target device. In the configuration of as or PS, in the configuration process, the role of user I/O, that is, three-state (high-impedance state). After the AP is configured, data[15..8] is dedicated to user-selectable pins.
Pins: 233 (DATA9), 234 (DATA10), 236 (DATA12), 224 (DATA14).

PADD[23..0]:
Type: I/o,output (AP)
Features: 24-bit address bus from Cyclone III to parallel flash.
Pins: 194 (PADD2), 196 (PADD3), (PADD4), 201 (PADD6), 202 (PADD7), 203 (PADD8), 207 (PADD12), 214 (PADD17), (PADD18), 222 (PADD19), 176 (PADD20).

Nreset:
Type: I/o,output (AP)
Function: Reset, low level active. When the Nrset is low, the parallel flash is reset.
Pin: Q240 Package None.

NAVD:
Type: I/o,output (AP)
Function: Address output, low level active. The drive NAVD is low-efficient when parallel flash reads and writes.
Pin: 174.

NOE:
Type: I/o,output (AP)
function: Parallel flash read enable foot, low level active. In the read operation, the drive NOE is low, enabling parallel flash output.
Pin: 168.

NWE:
Type: I/o,output (AP)
function: Parallel flash write is enable foot, low effective. In the write operation, the drive nwe is low, enabling parallel flash output.
Pin: 167.

Crc_error:
Type: I/o,output
Function: High-efficient, high-power indicates that the error detection circuit detected an error while configuring the SRAM bit. The pin is optional multiplexed and is used as a CRC error detection circuit to enable. The PIN can be set as an open-drain output in the Quartus II software.
Pin: 160.

DEV_CLRN:
Type: I/O (when option off) Input (if option on)
Function: Optional chip reset PIN, which allows all device registers to be covered clearly.
Pin: 145.

Dev_oe:
Type: I/O (when option off) Input (if option on)
function: Optional PIN allows the user to overwrite all devices in three states.
Pin: 144.

Init_done:
Type: I/o,output (Open-drain)
Function: This is a dual-purpose status pin that can be used as I/O when Ini_done is enabled. If enabled, the change process from low to high indicates that the device is transitioning into user mode. If the Int_done output is enabled, after configuration, the Int_done pin may not be used as an I/O port. This pin can be enabled by enabling the Init_done operation in the Quartus II software.
Pin: 159.

CLKUSR:
Type: I/o,uput
Function: Optional user-supplied clock input for synchronizing initialization of one or more devices. If this pin is not provided as a user-supplied configuration clock, it can be done as a user I/O foot. This pin can be enabled by opening the CLKUSR with the Quartus II software.
Pin: 164.

Dual-use differential and external memory interface pins

DIFFIO_[L,R,T,B][0..61][N,P]:
Type: I/O, TX/RX Channel
Function: Dual-purpose differential transmitter/receiver channel. These channels can be compatible with the transmission and reception of LVDS. P represents positive,n on behalf of negative. If differential signals are not applicable, these pins can be used as user I/O pins.

DQS[0..5][L,R,T,B]/CQ[1,3,5][L,R,T,B][#],DPCLK[0..11]:
Type: I/O, Dqs/cq, DPCLK
Features: Dual-use DPCLK/DQS pins can be connected to a global clock network with high fanout control signals such as clocks, asynchronous zeroing, presets, clock enable. It can also be used as an optional data strobe pulse signal for use in external memory interfaces. These pins drive a dedicated DQS phase shift circuit that allows for fine tuning of the input clock phase shift or flash to correct alignment needs to capture the clock edge of the data.

DQS[0..5][L,R,T,B]/CQ[1,3,5][L,R,T,B][#],CDPCLK[0..7]:
Type: I/O, Dqs/cq, CDPCLK
Features: Dual-use CDPCLK/DQS pins can be connected to a global clock network with high fanout control signals such as clocks, asynchronous zeroing, presets, clock enable. There is only one two cdpclk in each corner to feed the clock control block at a time. Other pins can be used as general purpose I/O pins. The CDPCLK signal generates more delay clock block control as they are being driven into the clock block before the control is multiplexed. It can also be used as an optional data strobe pulse signal for use in external memory interfaces. These pins drive a dedicated DQS phase shift circuit that allows for fine tuning of the input clock phase shift or flash to correct alignment needs to capture the clock edge of the data.

DQ[0..5][L,R,T,B]:
Type:/O, DQ
function: Optional data signal for the external memory interface.

DM[0..5][L,R,B,T][0..1]/BWS#[0..5][L,R,T,B]:
Type: I/O, dm/bws#
Function: When data masking pin, only need to write to DDR SDRAM and DDR2 SDRAM device. The BWS signal selection byte used by the Qdrii SRAM device is written to memory. The low level signal on the dm/bws# pin indicates that the write is valid. The memory driving the dm/bws# foot masks the results of the DQ signal.

ep3c16q240c8n Pin Description