Exynos 4412 eMMC configuration and usage, exynosemmc

Exynos 4412 eMMC configuration and usage, exynosemmc
/*************************************** **************************************** ** @ Author Maoxiao Hu * @ version V1.0.0 * @ date Feb-2015 ************************** **************************************** * *********** <COPYRIGHT 2015 ISE of shandong university> ******************* **************************************** * *******************/this article will improve and correct some minor errors from time to time, please go to the http://www.cnblogs.com/humaoxiao to see the latest version. Development Board: The 4412 best edition. Uboot: uboot-2014-10. EMMC on the Development Board: Samsung KLMxGxxEMx-B031 capacity 4 GB use eMMC 5.0 standard. EMMC Controller on exynos4412: The eMMC4.41 standard is used. Reference: see the end of this document. For more information, see [2.
This Samsung eMMC is compatible with the e. MMC 5.0 standard protocol, but the 4412 eMMC controller uses the e. MMC 4.4 standard. Is this combination not good for the moment. I. The most basic part of the clock 1.1 eMMC is the clock. eMMC supports a variety of clock types, such as 26 M 52 M HS200 HS400, of course, the more high-end eMMC supports the more clock modes. How do you know the clock Mode Supported by eMMC? Check [196] bytes of Extended CSD Register. Here, the B031 chip reads 0x57, so what is the meaning of each digit in 0x57, refer to section 7.4.54 of document [2]: After the contrast 0 1 2 4 6 bits is 1, that is, support HS400 HS200 HS52-DDR HS52 HS26, 4412 you can use any clock mode to operate eMMC. The clock rate and maximum transmission rate are also required for different modes. 1.2 The eMMC controller part finds the MMC controller Clock diagram from the CMU (Clock Management Unit) module, as shown in the following figure: the XusbXTI Clock source is used by default when the system is powered on, however, in actual use, the 24 m clock is far from enough. Therefore, we recommend that you select SCLKmpll_user_t as the clock source. For the selection method, see exynos 4412 clock configuration. Registers involved in the MUXmmc0-3:

CLK_SRC_FSYS

Address: 0x1003C240

Default Value: 0x00011111

Value after setting: 0x00066666

Registers involved in DIVmmc0-3 and DIVmmc0-3_pre:

CLK_DIV_FSYS1 & CLK_DIV_FSYS2 & CLK_DIV_FSYS3

Address: 0x1003C544 & 0x1003C548 & 0x1003C54C

Default Value: 0x00000000 & 0x00000000 & 0x00000000

Value: 0x09010901 & 0x09010901 & 0x09010901

In this way, when the MPLL is MHz, the first two-frequency division is followed by a very high frequency. Finally, the clock of the eMMC controller is 40 MHz. However, if the eMMC chip supports HS200 or HS400 high-speed mode, modify the Controller clock.

II. We all know that the eMMC is also hierarchical, from Class0 ~ For Class11, different classes support different command scopes. If you do not determine the Class, you cannot determine whether the issued command eMMC can respond correctly. Check that the CSD Register [95: 84] has a total of 12 bits. Here, the B031 reading is 0xF5 (11110101) and supports the Class0 Class2 Class4 Class5 Class6 Class7 instruction set. 3. confirm that the supported CMD commands can be launched from the supported Class instruction set. In this way, we can conclude that the commands not supported by this B031 are running 20 running 39 running 40 running 53 ~ 56. 4. CMD List 5. The CMD reply format first looks at the Resp column of the 4th column in the table above, representing the message that eMMC replies to the 4412 controller. Their meanings are as follows: 5.1 R1 reply format is 48bit in total, the maximum bit value is always 0, followed by 0 indicates that the message is sent from eMMC to the Controller, and then [45: 40] A total of 6 bits indicates which CMD (0 ~ 63), and then [39: 8] A total of 32 bits represent the status of the eMMC device, followed by CRC and RST bits. The meaning of Device status is as follows: 5.2 R1b reply format 5.3 R2 reply format R2 is used to reply to the three commands CMD2 9 10. When replying to CMD2 10, the content is the value of the CID register, when replying to limit 9, the content is the CSR register value. 5.4 R3 reply format 5.5 R4 reply format 5.6 R5 reply format 6. Some commonly used CMD 6.1 running 0 commands are used to reset eMMC. No reply: 6.2 CMD1 command to get the OCR register value of eMMC: here, the [31] bit is important. If it is 1, The eMMC reset is complete, the 0x40FF8080 reset is incomplete, and the 0xC0FF8080 reset is complete. 6.3 CMD2 command to obtain the CID register value of eMMC, a total of BITs, 16 bytes: The data read in the actual operation process: with the document (1) the CID registers in are completely consistent. 6.4 CMD3 this command is used to set the relative address of eMMC. The relative address is prepared for one bus to mount multiple eMMC. If there is only one eMMC, this command is meaningless. EMMC replies R1 to the Controller. The 6.5 limit 6 command is used to set the value of the Register in EXT_CSR in eMMC: [31: 26]: 0 []: see the table below, []: for the register index to be operated []: for the value of the Register to be written []: 0 []: If [] is 00b, the three meanings are as follows, 6.6 limit 7 this command is used to set the eMMC state, because after eMMC is reset with limit 0, eMMC is in the idle or pre_idle state. If data transmission is required, eMMC must be placed in the transfer_state, 7 is the role. EMMC replies R1 to the Controller. 6.7 listen 8 this command is used to obtain the value of EXT_CSD. Although it returns to R1, the 512-byte value of EXT_CSD will be read and stored in the memory, then, you can analyze the parameters and statuses currently supported by eMMC based on the data. Note that because EXT_CSD is a register group introduced after eMMC4, this command is issued to read EXT_CSD only after the eMMC version is determined to be greater than 4. 6.8 ipv13 requires eMMC to send its own status. VII. Operation Sequence after eMMC is powered on, it needs to be reset first and then reset to 0. Then eMMC will automatically reset the busy status and send CMD1 cyclically to detect the busy status. When the busy status ends, eMMC enters the ready status, then sends CMD2 for authentication (obtain CID), then sends CMD3, then eMMC enters the stby status, and finally enters the transfer status using sequence 7, in this case, you can use limit 16 to read a single block and segment 17 to read multiple blocks. The above is the general operation order, including the most critical commands. Of course, you can also insert some unnecessary commands, such as limit 6 and limit 13. For detailed status switching diagrams, see references: [1] KLMxGxxEMx-B031 Spec [2] JESD84-B50 (Note: eMMC 5.0 standard protocols)