Fault Code Description quick query table debug code

Fault Code Description quick query table debug code

1. Special codes "00" and "FF" and other start codes may occur in three situations:

① If "00" or "FF" is displayed after a series of other codes, the motherboard is OK.

② If no error is set in CMOS, the non-serious fault will not affect the BIOS self-check, and "00" or "FF" will eventually occur ".

③ The "00", "FF", or other starting Code does not run when the server is started and does not change.

2. This table is sorted by code value from small to large, and the order of outgoing codes in the card is not fixed.

3. The undefined code table is not listed.

4. For different BIOS (Common AMI, award, Phoenix), the same code represents different meanings, therefore, you should find out which type of BIOS the computer you are detecting belongs to. You can check your computer user manual or directly view it from the BIOS chip on the motherboard, you can also see it directly when you start the screen.

5. There are a few PCIe slots for the main board, only the first part of the code appears, but the ISA slot has a complete self-check code output. At present, the ISA slot with a few original installation boards has no code output, while the PCI slot has complete code output. Therefore, when you fail to check the code, switch the dual-slot card to another slot. In addition, different PCIe slots of the same motherboard, some of which have complete code output. For example, the dell810 motherboard only has a PCIe slot close to the CPU and has complete code display, it changes until "00" or "FF", while other slots go to "38" without changing.

6. The time required for resetting the signal is not necessarily the same as that for PCI. Therefore, ISA may start to issue the code, but the reset light of PCI is still disabled, so the PCI code stops at the start code.

Code Award bios AMI biosphoenix BIOS or Tandy 3000 BIOS

00: the system configuration is displayed. The ini19 boot loader will be controlled. Http://www.400gb.com/file/70471256

01 processor Test 1. Verify the processor status. If the test fails, the loop is infinite. The test of the Processor register is about to begin, and the unshielded interrupt is about to be stopped. The CPU register test is in progress or fails.

02 determine the diagnosis type (normal or manufacturing ). If the Keyboard Buffer contains data, it will become invalid. Stopovers cannot block interruptions; start with a delay. CMOS writing/reading is in progress or fails.

03 clear the 8042 keyboard controller and issue the testkbrd command (AAH) power-on delay. The rom bios check component is in progress or fails.

04 reset the 8042 keyboard controller and verify testkbrd. Keyboard controller soft reset/power-on test. The test of the programmable interval timer is in progress or fails.

05 if the manufacturing test is repeated for 1 to 5, 8042 control status can be obtained. Determined soft reset/power-on; Rom will be started soon. If the preparation is in progress or fails at the beginning of DMA.

06 make the circuit chip initial preparation, stop the video, parity, DMA circuit chip, and clear the DMA circuit chip, all page registers and CMOS stop bytes. The Rom has been started to calculate the total rom bios check and check whether the keyboard buffer is cleared. The DMA initial Page register read/write test is in progress or fails.

07 processor Test 2. Verify the CPU register operation. The rom bios check sum is normal, the keyboard buffer is cleared, and the bat (basic guarantee test) command is sent to the keyboard.

08 enable the CMOS timer for initial preparation, and update the cycle of the timer normally. A bat command has been issued to the keyboard, which is about to be written. The ram Update Check is in progress or fails.

09eprom check sum and must be equal to zero to pass. Verify the basic guarantee test for the keyboard, and then verify the Keyboard Command byte. The first 64 k ram test is in progress.

0a used the video interface for initial preparation. The byte code of the keyboard command is sent to write the byte data of the command. The first 64 k ram chip or data cable failed and moved.

0 B test 8254 channel 0. Write the keyboard controller command byte to issue the block/UNLOCK Command on pins 23 and 24. The first 64kram odd/even logic failure.

0C test 8254 Channel 1. The keyboard controller pins 23 and 24 have been blocked/unlocked; The NOP command has been issued. The address line of the first 64kran is faulty.

0d1, check whether the CPU speed matches the system clock. 2. Check whether the programmed value of the control chip meets the initial setting. 3. video channel test. If the test fails, the speaker honks. The NOP command has been processed; test the CMOS to stop the register. The first 64 k ram parity failure

0e test the CMOS shutdown byte. CMOS stops register read/write tests. The sum of CMOS checks is calculated. Initialize the input/output port address.

0f test the extended CMOS. The sum of the calculated CMOS checks is written into the diagnostic byte; the initial preparation starts for CMOS. Http://www.400gb.com/file/70471256

10 test the DMA channel 0. The CMOS has been initially prepared, and the CMOS Status Register is about to make initial preparations for the date and time. The first 64 k ram 0th-bit fault.

11. Test DMA Channel 1. The CMOS Status Register has been initially prepared to stop the DMA and interrupt controllers. The first 64dk Ram 1st-bit fault.

12. Test the DMA page register. Disable DMA controller 1 and interrupt controller 1 and 2; Prepare the video display and port B for initial preparation. The first 64dk Ram 2nd-bit fault.

13. Test the 8741 keyboard controller interface. The video monitor has been disabled, and port B has been initially prepared. Circuit Chip initialization/memory automatic detection will be started soon. The first 64dk Ram 3rd-bit fault.

14. Test the memory update trigger circuit. The detection of Circuit Chip initialization/memory ends automatically; 8254 the timer test is about to begin. The first 64dk Ram 4th-bit fault.

15 system memory at the beginning of the test for 64 KB. The 2nd-channel timer is half tested; The 8254-channel timer is about to complete the test. The first 64dk Ram 5th-bit fault.

16. Create the interrupt vector table used by 8259. 2nd the channel timer test is complete; 8254 the channel timer is about to complete the test. The first 64dk Ram 6th-bit fault.

17. Tune video input/output. If the video BIOS is installed, enable it. 1st the channel timer test is complete; 8254 the channel timer is about to complete the test. The first 64dk Ram 7th-bit fault.

18. Test the video memory. If the selected video BIOS is installed, it can be bypassed. 0th the test of the channel timer is complete; the memory update is about to begin. The first 64dk Ram 8th-bit fault.

19. Test the 1st-channel Interrupt Controller (8259) shielding bit. The storage has been updated, and the storage is updated. The first 64dk Ram 9th-bit fault.

1A test 2nd-channel Interrupt Controller (8259) shielding bit. The memory update line is being triggered, which is about to check the 15 microsecond access/disconnection time. The first 64dk Ram 10th-bit fault.

1B test the CMOS battery level. The test of memory Update Time is completed in 30 microseconds. The basic 64 K memory test is about to begin. The first 64dk Ram 11th-bit fault.

Total number of CMOS checks for 1C testing. The first 64dk Ram 12th-bit fault.

1D adjusts the CMOS configuration. The first 64dk Ram 13th-bit fault.

1e determine the size of the system memory and compare it with the CMOS value. The first 64dk Ram 14th-bit fault.

1f test 64 K memory to a maximum of 640 K. The first 64dk Ram 15th-bit fault.

20. Fixed 8259 interrupt bits are measured. Start the basic 64 K memory test; the address line will be tested soon. The slave DMA register test is in progress or fails.

21 maintain the unshielded interrupt (NMI) bit (parity or input/output channel check ). Pass the address line test, which will trigger parity. The master DMA register test is in progress or fails.

22. Test the interrupt function of 8259. End trigger parity; the serial data read/write test will begin. The main interrupt shielding register test is in progress or fails.

23. Test the protection mode 8086 virtual mode and 8086 page mode. The basic 64 K serial data read/write test is normal, and any adjustment before the vector Initialization is about to be interrupted. The slave interrupt blocker test is in progress or fails.

Extended memory of more than 1 MB is measured at 24. Any adjustment before vector Initialization is complete, and the initial preparation of the interrupted vector is about to begin. Set the es segment address register to the memory high-end.

25 test all memory after the first 64 K. The initial preparation of the interrupt vector is completed. The 8042 input/output port is read for the rotary intermittent start. Http://www.400gb.com/file/70471256loading failure is in progress or in bad spirits.

26. Exceptions in the protection mode test. Read the 8042 input/output port, which is about to make the initial preparation for the global data. Enable the A20 address line to input addressing parameters.

27 determine the control or shield RAM for ultra-high-speed buffer storage. The initial preparation for all 1 data is complete, and any initial preparation after the interrupt vector is performed. The keyboard controller test is in progress or fails.

28 determine the control of ultra-high speed buffer memory or a special 8042 keyboard controller. The initial preparation after the interrupt vector is completed; the monochrome mode will be adjusted. CMOS power supply fault/check sum calculation in progress.

29 The monochrome method has been adjusted, and the color method will be adjusted soon. Check whether the CMOS configuration is valid.

2a make initial preparations for the keyboard controller. The color method has been adjusted to trigger parity before Rom testing. Leave the 64 K basic memory empty.

2b make initial preparations for the disk drive and controller. Trigger parity ends; Any adjustments required before any video Rom check will be controlled. The screen memory test is in progress or fails.

2c checks the serial port for initial preparation. Process the video ROM control. You will view and control the available video Rom. Initial Screen Preparation is in progress or failed.

Inspect the parallel port in 2D mode and make the initial preparation. You have completed any video ROM control and will be able to control any other operations after the video Rom reply control is completed. The screen scan test is in progress or fails.

2e make initial preparations for the hard disk drive and controller. The process is restored after the video Rom is controlled. If no memory or VGA is found, the display memory read/write test is required. The detection video Rom is in progress.

2f detects the math coprocessor and prepares it for initial preparation. No memory/VGA found; Display memory read/write test is about to begin.

30. create basic memory and extended memory. Read/write tests through the Display memory; scanning will be performed soon. The screen can work.

31. Check the ROM selected from c800: 0 to efff: 0 and make it an initial preparation. The Display memory read/write test or scan check fails, and another display memory read/write test is coming soon. A monochrome monitor can work.

32 programming for I/O chips such as COM/LTP/FDD/sound device on the motherboard makes it suitable for setting values. A read/write test is performed on another display memory, but a scan check is performed on another display. Color Monitor (40 columns) can work.

33. The video monitor check is complete. The regulating switch and the actual plug-in card will be used to check the off type of the monitor. Color Monitor (80 columns) can work.

34. The display adapter has been inspected. The display mode will be adjusted. The timer ticking Interrupt Test is in progress or fails. Http://www.400gb.com/file/70471256

35. Check the BIOS Rom data zone. The shutdown test is in progress or fails.

36. Check the BIOS Rom data area. The power-on information cursor will be adjusted. A-20 failure in the door circuit.

37. The cursor setting for identifying power-on information has been completed. The power-on information will be displayed soon. Accidental interruption in protection mode.

38. The power-on information is displayed. A new cursor is to be read. RAM testing in progress or address fault> ffffh.

39. The cursor position is read and saved. A reference string is displayed.

3A reference information string display ends; <ESC> information is displayed soon. Interval timer Channel 2 test or failure.

3b uses an opti circuit chip (only 486) to enable the auxiliary ultra-high speed buffer storage for initial preparation. <ESC> information displayed; virtual mode, memory test is about to begin. The calendar clock test calculated by day is in progress or fails.

3C creates a flag that allows access to the CMOS settings. The serial port test is in progress or fails.

3D initialization keyboard/PS2 mouse/PNP device and total memory node. Parallel Port testing is in progress or fails.

3E tries to enable the L2 cache. The math coprocessor test is in progress or fails.

40 virtual testing has been started; testing will be conducted from video storage. Adjust the CPU speed to make it exactly match with the peripheral clock.

41. The interrupt is enabled. initialize the data so that can detect the memory transform (Interrupt Controller or poor memory) and restore the data from the video memory test. The descriptor table will be prepared soon. System plug-in board selection failure.

42. Enter setup in the displayed window. The descriptor table is ready; virtual storage testing will be performed. Extended cmos ram fault.

43 If the plug-and-play BIOS is used, the serial port and parallel port are initialized. Enter the virtual mode. The diagnosis method will be interrupted.

44 interruptions have been implemented (for example, the diagnosis switch has been enabled; data is about to be initially prepared to check the memory for 0-0 conversion .) BiOS interruption initialization.

45 initialize the math coprocessor. The data has been initially prepared; the memory will be checked for 0-0 conversion and the size of the system memory will be identified.

46. The test memory has been returned. The memory size is calculated and will be written to the page to test the memory. Check the read-only memory rom version.

47 will be on the extended storage trial Writing Page; will be written to the basic 640k storage page. Http://www.400gb.com/file/70471256

48 The basic memory has been written to the page; the memory above 1 MB will be determined. Video check and CMOS reconfiguration.

49 locate and test the memory below 1 bm; Determine the memory above 1 MB.

4A locate and test the memory larger than 1 MB. the BIOS Rom data zone will be checked soon. Initialize the video.

The test in the 4bbiosrom data zone is complete. The <ESC> check is to be completed and the memory above 1 MB is cleared for the soft reset.

4c clears memory larger than 1 MB (soft reset). Memory larger than 1 MB will be cleared. Video BIOS Rom will be shielded ..

4D has cleared more than 1 MB of memory (soft reset); the memory size will be saved.

4e if an error is detected, the error message is displayed on the monitor, and the customer waits for the <F1> key to continue. Start the memory test: (no soft reset); the first 64 K memory test will be displayed soon. Display copyright information.

4f reads and writes soft and hard disk data for DOS boot. Start to display the memory size. Testing the memory will update it; serial and random memory testing will be performed.

50. Save the CMOS value in the current BIOS monitoring time zone to CMOS. Complete the memory test for less than 1 MB, that is, the size of High-Speed memory for further locating and masking. Send the CPU type and speed to the screen. 51 Test memory of 1 MB or more.

52 Initialize all ISA read-only memory ROM and assign IRQ to PCI. The memory test of 1 MB or more has been completed. You are about to return to the actual address. Go to the keyboard detection page.

53 if you are not using the plug-and-play bios, initialize the serial port, parallel port, and set the time value. The size of the CPU registers and memory will be stored in the real address mode.

54. The address method is enabled successfully. The register is to be restored when preparation is stopped. Scan "Strike key"

Register 55 is restored and the address line of the gate circuit A-20 will be disabled.

56 The address line of the A-20 was disabled successfully; the BIOS Rom data zone will be checked soon. The keyboard test is complete.

Half of 57biosrom data zone check; continue.

58biosrom's data zone check is complete. <ESC> information is cleared. The test is not interrupted.

59. <ESC> information is cleared. Information is displayed. The DMA and interrupt controller testing will begin.

5a. Press the "F2" key to set the display. 5b. Test the basic memory address. 5C. Test the basic memory of 640k.

60 set the hard drive Boot Sector virus protection function. Pass the DMA page register test; the video memory will be verified soon. Test extended memory.

61. The system configuration table is displayed. The video memory test is complete. The DMA #1 basic register test is coming soon.

62 start to use the 19h interrupt for system boot. Test the basic register of DMA #1; the test of the register of DMA #2 will be carried out soon. Test the extended memory address line.

63 pass the DMA #2 basic register test; the BIOS Rom data zone will be checked soon.

The 64biosrom data area is half checked and continues. 65 BIOS Rom data zone check is complete; DMA device 1 and 2 will be programmed.

The 66dma device 1 and 2 programming ends; the 59 Interrupt Controller will be used for initial preparation. Cache registry for optimized configuration.

678259 the initial preparation is complete. The keyboard test is about to begin. 68. Make the external cache and CPU internal cache both work at http://www.400gb.com/file/70471256.

6a. Test and display the external cache value. 6c. Display blocked content. 6e. The accessory configuration information is displayed.

70. The detected error code is sent to the screen. 72. Check whether the configuration is correct. 74. Test the real-time clock. 76. Scan for keyboard errors. 7A. Lock the keyboard.

7c. Set the hardware interrupt vector. 7E. test whether a mathematical processor is installed.

At the beginning of the 80 keyboard test, the system is clearing and checking whether the key is stuck. The keyboard will be restored soon. Disable the programmable input/output device.

81. Find out the key that gets stuck with the keyboard recovery error. The test command for the keyboard control port will be issued soon.

82. The test of the keyboard controller interface is completed, which is about to write command bytes and make initial preparations for the loop buffer. Detect and install the fixed RS232 interface (serial port ).

83 the command byte has been written, and the initial preparation of global data has been completed. check whether there is a key lock.

84 check whether there are locked keys. Check whether the memory is out of match with CMOS. Detect and install fixed parallel ports.

85 check the memory size; a soft error and password or bypass arrangement will be displayed.

86 the password has been checked; the program before the bypass arrangement will be executed. Re-enable the programmable I/O device and check whether there is a conflict with the fixed I/O.

87. Programming before the arrangement is completed; the CMOS arrangement will be performed.

88 recover the screen from the CMOS schedule; subsequent programming is coming soon. Initialize the BIOS data zone.

89. After the arrangement is completed, the power-on screen information will be displayed.

8A displays the first screen information. Initialize the extended BIOS data zone.

8b displays information: the main and video BIOS will be blocked soon.

The 8C successfully shields the main and video bios and will start programming any options after CMOS. Initialize the software drive controller.

Any option programming has been arranged for 8d, then check the slide mouse and perform initial preparation. Http://www.400gb.com/file/704712568e detects the mouse and restores the mouse when it is completed.

The 8f disk has been checked. The disk will be initially prepared and then equipped with a soft disk. The 90 soft disk configuration is complete. The existence of the hard disk will be tested. Initialize the hard disk controller.

91. The test of the hard disk is completed, and then the hard disk is configured. Initialize the local bus hard drive controller.

92. The hard disk configuration is complete. the BIOS Rom data zone will be checked soon. Go to user Path 2.

Half of 93biosrom's data zone has been checked; continue.

The data zone check of 94biosrom is completed, that is, the size of the base and extended memory are adjusted. Close the A-20 address line.

95 adjust the memory size based on the support of the mouse and hard disk type 47; Display memory will be verified soon.

96 tests show that the memory is restored; the initial preparation before the c800: 0 select ROM control will be performed. Clear the "es segment" registry.

97c800: 0 any ROM control before any initial preparation ends, and then check and control the optional Rom.

98 the control of any Rom is completed; Any processing required after the control of any Rom reply will be performed. Find Rom selection.

99 any initial preparation required after the ROM test is selected; the data zone or printer basic address for which the timer is to be created.

9A return operation after the timer and printer basic address are set; that is, the RS-232 basic address is set. Select the shield Rom.

9b returns after the RS-232 base address; the initial preparation for a coprocessor test is coming soon.

Before the 9C coprocessor test, the initial preparation is completed. Then, the coprocessor is made initial preparation. Establish power saving management.

9d coprocessor is ready for initial preparation. Any initial preparations after the coprocessor test will be made.

9e completes the initial preparation after the coprocessor, and checks the extended keyboard, keyboard identifier, and number lock. Hardware interruption is enabled.

9f has checked the extended keyboard, tuned the identification mark, and the number lock is connected or disconnected. A keyboard recognition command will be issued.

A0 issues a keyboard recognition command; the keyboard recognition mark will be restored soon. Set the time and date. The A1 keyboard recognition mark is restored, and then the high-speed buffer memory test is conducted.

A2 high speed buffer memory test is complete; any soft errors will be displayed soon. Check the keyboard lock. Http://www.400gb.com/file/70471256 A3 Soft Error display completed; the keyboard hit rate will be adjusted.

A4 adjust the keyboard hit rate to determine the memory wait state. Repeat input rate Initialization on the keyboard.

A5 memory wait status is set up; then the screen is cleared. The A6 screen has been cleared; it is about to enable parity and unblocking interruption.

A7 unshielded interruptions and parity are enabled; any initial preparation required to control the optional ROM at e000: 0 is coming soon.

The initial preparation of the A8 control Rom before e000: 0 is completed, and any initial preparation required after e000: 0 will be controlled. Clear the "F2" Key prompt.

A9 is returned from the control e000: 0 Rom, and any initial preparation required after the control e000: 0 is selected.

The initial preparation of AA is completed after the optional Rom is controlled at e000: 0. The system configuration is displayed. Scan for the "F2" key.

AC. Go to settings. AE. Clear the power-on self-check mark. Non-critical errors of B0. B2. power-on self-check is complete. Prepare to go to the operating system boot.

B4. a buzzer. B6. password detection settings (optional ). B8. clear all description tables. BC. Clear the check value.

The default value of the be program enters the control chip, which complies with the default value table of the modulated binary program. Clear the screen (optional ).

BF test the CMOS creation value. Detect viruses and prompt for data backup.

C0 initializes the cache. Use 19 pilot disconnections. C1 memory self-check. Find the "55" "AA" mark in the boot sector. C3 first 256k memory test ..

C5 copies the BIOS from the ROM for fast self-check. C6 high-speed cache self-check ..

CA detects the micronies overspeed buffer memory (if any) and prepares it for initial preparation ..

CC shutdown unshielded interrupt processor ..

Exceptions unexpected by EE processors ..

FF controls the ini19 boot loader and the motherboard is OK.

More computer knowledge tutorials and computer maintenance knowledge are as follows:

Computer Maintenance internal information: http://www.400gb.com/file/70471256

[Computer tutorial] detailed diagram of System Installation Process

Tutorial] computer learning 2.0

[Experience] _ computer repair (you can open your own computer repair shop after reading it !)

4 years experience in computer maintenance

According to these eight items, it is difficult to slow down the computer.

What do every project in Bois mean?

Computer FAQ and fault 1000 Cases

Full-Process Computer Management and Maintenance Diagram

Laptop repair manual

Six commonly used software that damages hard disks for a long time!

Common troubleshooting methods for computer faults

Analysis of common causes of crashes

Computer Fault repair Overview

Analysis of computer crash

Computer Maintenance Skills

Computer Maintenance Training Materials

Computer Repair Quick Start

Computer Maintenance Experience and Maintenance Experience

Apsaravideo for AI

Computer Assembly tutorial

Make your computer faster

Easily eliminate computer faults

System Repair Method 6

Hardware materials and knowledge

View computer configurations

Common hard disk faults

Basic hardware knowledge

How to learn computer repair

Tips and precautions for purchasing host accessories

Self-taught computer repair, familiar with several times you are a master !!!

Latest computer motherboard Fault Diagnosis card query table

Motherboard repair full learning Manual

 

 

Fault Code Description quick query table debug code