Fifth Chapter S5PV210 Hardware structure

Source: Internet
Author: User

This chapter is part of the hardware and describes the hardware structure of s5pv210, which includes:

The s5pv210 microprocessor, a 32-bit microprocessor with low power features, provides high-performance microprocessor solutions for mobile devices and general applications. It integrates the arm CORTEX-A8 Core, implements the ARM architecture v7a, and supports peripheral devices.

Gpio dedicated register--port Group Control Register, port Group Gpao Control Register, Port Group GPA1 Control Register, GPIO interrupt control register.

The PWM timer--(pulse width modulation) timer is used to generate internal interrupts to the arm subsystem, and the s5pv210 consists of 5 32-bit PWM timers.

DMA controller-Direct access to memory. It includes two key points: one is memory-memory (DMA_MEM), and the other is peripheral-to-memory transmission.

UART Serial Interface-an asynchronous receive/send device that provides four separate serial I/O ports, all of which operate in interrupt or DMA mode. The UART controller can generate interrupts or DMA requests between the CPU and the UART to transmit data.

ADC and Touch screen interface--analog-to-digital converter and touch screen interface, touch screen interface can control the selection of touch-screen contact for XY coordinate conversion, it includes touch contact control logic and interrupt-generating logic ADC interface logic.

SPI interface, IIC bus interface in the sophomore contact, have some understanding.

Fifth Chapter S5PV210 Hardware structure

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