[Finishing] An interesting question about the latch (latch)

Origin

Today exaggeration forum, suddenly found a question about latch, because of D flip-flop and latch still have some questions, click into, a look really some meaning, also have learning meaning, so this article was born. Shout out the slogan ~just note it.

Interesting problem diagram

Two questions.

• The circuit described above on the left, if not added else q<=0; , will generate latch?
• The circuit described above on the right, if not added else q<=0; , will generate latch?

Brainstorming

On the forum there are a lot of great gods and predecessors, a few answers quite good, has a very strong guiding significance, people can't help thinking, and then began to think silently life. Poof, not much to say, we look at the reference. (There are limitations, OH, here thanked the original greatly to provide their own views)

old Ruan (a look at the name will know is an old fritters, manual funny):

• Sequential circuit, generate trigger, trigger is have the enable end, the data is not changed when the energy side is invalid, this is the characteristics of the trigger.
• The combination logic, because the data to remain unchanged, can only be saved through the latch.
• The first code, because it is a timing logic, generates a trigger that saves data when enable is not valid. Not related to latches.
• The second code is that when enable is low, the data is not changed, so a latch is generated.

Looks very reasonable, the analysis of the more detailed, this issue in detail the difference between the two, very instructive.

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Chengroc(the ID of the English alphabet, it looks like it is the surname, it is called Mr. Cheng, what you say two Cheng not the same, oops don't care about these details, see below):

• Latch is actually simpler than the DFF structure.
• If you can control timing in digital design, consciously using latch is not a must. But it also increases the amount of time behind the timing analysis. Front-end design and back-end timing analysis to pass more information, but also easy to miss, but also can do well.
• is afraid to use the latch unconsciously, for example, this would like to achieve a combination of logic function, but because the condition has not been written complete led to the emergence of latch, the back end another negligence, resulting in completely uncontrolled.
• And with DFF to achieve data retention, the problem is much simpler.

Mr. Cheng simply explained the next latch and DFF, although not in depth, but for me now, well enough, and then I go deep to see D trigger and latch some knowledge points.

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walkman416(a combination of letters and numbers, a good common combination, call him Walkman):

• Personal understanding: The so-called generate latch is actually for using always statements to describe a combinatorial logic, because if the description of timing logic always use a clock or clock + reset as a sensitive list condition, the generated circuit is usually composed of logic +dff; The sensitive list must not have a clock reset, but a combination of logic input signals. In FPGA design, avoiding the use of latch is not conducive to timing analysis and simulation. Upstairs mentioned latch than DFF province resources, this in the FPGA design is actually good, because in the FPGA DFF is a dedicated hardware resources, and the number is more.

• When using always to describe combinatorial logic, a good habit is to use always @ (*) as a sensitive list, and to check that each branch has a definite assignment to avoid generating latch.

Gee said really good, I also want to summarize next, Walkman, Nice!

Comprehension Summary

1. Look at always sensitive information, if it is the edge trigger, then for the timing logic, this problem does not produce latch. But I'm obsessive-compulsive. Hello, write if do not write else are bullying ah hello, for the integrity of the code or else to fill the good, can write can else ; also write else q<=q; , in short, fill on the good, so maybe there are other benefits I do not know, follow-up know again.
2. FPGA now to latch understanding is not deep enough, or less use good, also try to avoid latch, after all, and ASIC some difference, DFF in FPGA can be regarded as a kind of basic logic.
3. Walkman says well, when combining logic, you can use it [email protected](*) as a sensitive list, and check that each else or case branch has a definite assignment.

Hope to read you have help, welcome to explore. If there is anything wrong, you must not be polite to reply vigorously shoot bricks ~

[Finishing] An interesting question about the latch (latch)